Author: uwe
Date: 2008-10-14 12:14:06 +0200 (Tue, 14 Oct 2008)
New Revision: 925
Modified:
coreboot-v3/superio/fintek/f71805f/dts
Log:
Fix incorrect and incomplete Fintek F71805F dts. Some LDNs got mixed
up in the dts, some LDNs were missing.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Corey Osgood <[EMAIL PROTECTED]>
Modified: coreboot-v3/superio/fintek/f71805f/dts
===================================================================
--- coreboot-v3/superio/fintek/f71805f/dts 2008-10-14 10:13:24 UTC (rev
924)
+++ coreboot-v3/superio/fintek/f71805f/dts 2008-10-14 10:14:06 UTC (rev
925)
@@ -20,33 +20,44 @@
{
device_operations = "f71805f_ops";
+
/* Floppy */
- floppydev = "0x0";
+ floppydev = "0";
floppyenable = "0";
floppyio = "0x3f0";
floppyirq = "6";
floppydrq = "2";
- /* Parallel port */
- ppdev = "1";
- ppenable = "1";
- ppio = "0x378";
- ppirq = "7";
-
- /* Serial Port 1 */
- com1dev = "2";
- com1enable = "1";
+ /* COM1 */
+ com1dev = "1";
+ com1enable = "0";
com1io = "0x3f8";
com1irq = "4";
- /* Serial Port 2 */
- com2dev = "3";
- com2enable = "1";
+ /* COM2 */
+ com2dev = "2";
+ com2enable = "0";
com2io = "0x2f8";
com2irq = "3";
+ /* Parallel port */
+ ppdev = "3";
+ ppenable = "0";
+ ppio = "0x378";
+ ppirq = "7";
+
/* Hardware Monitor */
- hwmdev = "0xb";
+ hwmdev = "4";
hwmenable = "0";
- hwmio = "0xec00";
+ hwmio = "0x295";
+ hwmirq = "0"; /* TODO? */
+
+ /* GPIO */
+ gpiodev = "6";
+ gpioenable = "0";
+ gpioirq = "0"; /* TODO? */
+
+ /* PME */
+ pmedev = "10";
+ pmeenable = "0";
};
--
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