On Thu, Oct 16, 2008 at 9:36 AM, Rudolf Marek <[EMAIL PROTECTED]> wrote:
> The reason why exactly this needs to be handled in rom stage is that the > shadow registers needs to be filled _before_ PCI reset, because > PCI reset will force the internal microcontroller to reload with this > configuration. Its not much documented, only in programming guide, > and there is just assembly code and some strange English ;) they really > mention that the controller should be reloaded when the device enters D0 via > PCIRST#. Dont know if for example some ->D3 and ->D0 transition will work or > not. > FWIW, this is what stage2 is for in v3. Just this kind of thing. ron -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
