These changes add support for utility functions to dump routing. They also add a mainboard.c for serengeti that will call them. Interesting note: adding a set of mainboard ops and mainboard.c for mainboards is trivial: create file, add to makefile, add property to mainboard dts, done. A good sign that we got something right. Index: northbridge/amd/k8/Makefile Add util.c to stage2 files. Index: northbridge/amd/k8/util.c Utility to print routing registers. Index: mainboard/amd/serengeti/mainboard.c new mainboard.c -- currently, only use is that the phase6 init calls the code to show all routing registers as a debug function, but it shows how to use a stage2 mainboard file. Index: mainboard/amd/serengeti/Makefile add mainboard.c to makefile. Index: mainboard/amd/serengeti/dts add device_operations="serengeti"; property, so we link in to mainboard device ops. Index: include/arch/x86/amd/k8/k8.h k8.h: add defines for start and end of routing registers. Index: include/arch/x86/amd/k8/k8.h =================================================================== --- include/arch/x86/amd/k8/k8.h (revision 937) +++ include/arch/x86/amd/k8/k8.h (working copy) @@ -131,6 +131,18 @@ #define HTIC_INIT_Detect (1<<6) /* Function 1 */ +/* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at + * 0x78, 0xb8, and 0xd8 + */ +#define DRAM_ROUTE_START 0x80 +#define DRAM_ROUTE_END 0x78 +#define MMIO_ROUTE_START 0x80 +#define MMIO_ROUTE_END 0xb8 +#define PCIIO_ROUTE_START 0xc0 +#define PCIIO_ROUTE_END 0xd8 +#define CONFIG_ROUTE_START 0xe0 +#define CONFIG_ROUTE_END 0xec + #define PCI_IO_BASE0 0xc0 #define PCI_IO_BASE1 0xc8 #define PCI_IO_BASE2 0xd0 Index: mainboard/amd/serengeti/dts =================================================================== --- mainboard/amd/serengeti/dts (revision 939) +++ mainboard/amd/serengeti/dts (working copy) @@ -19,6 +19,7 @@ */ /{ + device_operations="serengeti"; mainboard_vendor = "AMD"; mainboard_name = "Serengeti"; cpus { }; Index: mainboard/amd/serengeti/Makefile =================================================================== --- mainboard/amd/serengeti/Makefile (revision 937) +++ mainboard/amd/serengeti/Makefile (working copy) @@ -49,7 +49,7 @@ $(src)/lib/clog2.c -STAGE2_MAINBOARD_SRC = +STAGE2_MAINBOARD_SRC = mainboard.c $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" Index: mainboard/amd/serengeti/mainboard.c =================================================================== --- mainboard/amd/serengeti/mainboard.c (revision 0) +++ mainboard/amd/serengeti/mainboard.c (revision 0) @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void show(struct device *dev) +{ + void showallconfig(int level, struct device *dev); + struct device *f1; + + f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + + showallconfig(BIOS_DEBUG, f1); + +} + +struct device_operations serengeti = { + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_AMD, + .device = 1}}}, + .constructor = default_device_constructor, + .phase6_init = show, +}; Index: northbridge/amd/k8/util.c =================================================================== --- northbridge/amd/k8/util.c (revision 0) +++ northbridge/amd/k8/util.c (revision 0) @@ -0,0 +1,203 @@ +/* + * K8 northbridge utilities (dump routing registers) + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Vincent Legoll + * Original Python code + * Convert to c (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BITS(r, shift, mask) (((r>>shift)&mask)) + +/** + * return "R" if the register has read-enable bit set + */ +static char *re(u32 i) +{ + if (i & 1) + return "R"; + else + return ""; +} + +/** + * return "W" if the register has read-enable bit set + */ +static char *we(u32 i) +{ + if (i & 1) + return "W"; + else + return ""; +} + +/** + * return a string containing the interleave settings. + */ +static char *ileave(u32 base) +{ + switch((base >> 8) & 7) { + case 0: return "No interleave"; + case 1: return "2 nodes"; + case 3: return "4 nodes"; + case 7: return "8 nodes"; + default: return "Reserved"; + } +} + +/** + * Return the node number. + * For one case (config registers) these are not the right bit fields. + */ +static int node(u32 reg) +{ + return BITS(reg, 0, 7); +} + +/** + * Return the link number. + * For one case (config registers) these are not the right bit fields. + */ +static int link(u32 reg) +{ + return BITS(reg, 4, 3); +} + + +/** + * Print the dram routing info for one base/limit pair. + * Show base, limit, dest node, dest link on that node, read and write enable, and + * interleave information. + * @param level printing level + * @param which Register number + * @param base Base register + * @param limit Limit register + */ +void showdram(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "%08x-%08x, ->(%d), %s, %s, %s, %d", ((base&0xfff0000)<<8), ((lim&0xffff0000<<8))+0xffffff, node(lim), re(base), we(base), ileave(base), (lim>>8)&3); +} + +/** + * Print the config routing info for a config register. + * Show base, limit, dest node, dest link on that node, read and write enable, and + * device number compare enable + * @param level printing level + * @param which Register number + * @param reg config register + */ +void showconfig(int level, u8 which, u32 reg) +{ + /* don't use node() and link() here */ + printk(level, "Base %02x Lim %02x ->(%d,%d),%s %s CE %d\n", BITS(reg, 24, 0xff), BITS(reg, 16, 0xff), + BITS(reg, 4, 7), BITS(reg, 8, 3), re(reg), we(reg), BITS(reg, 0, 4)); +} + +/** + * Print the pciio routing info for one base/limit pair. + * Show base, limit, dest node, dest link on that node, read and write enable, and + * VGA and ISA Enable. + * @param level printing level + * @param which Register number + * @param base Base register + * @param limit Limit register + */ +void showpciio(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "%08x-%08x, ->(%d,%d), %s, %s,VGA %d ISA %d", + BITS(base, 12, 0x3fff), BITS(lim, 12, 0x3fff), node(lim), link(lim), + re(base), we(base), BITS(base, 4, 1), BITS(base, 5, 1)); +} + +/** + * Print the pciio routing info for one base/limit pair. + * Show base, limit, dest node, dest link on that node, read and write enable, and + * CPU Disable, Lock, and Non-posted. + * @param level printing level + * @param which Register number + * @param base Base register + * @param limit Limit register + */ +void showmmio(int level, u8 which, u32 base, u32 lim) +{ + printk(level, "%08x-%08x, ->(%d,%d), %s, %s, CPU disable %d, Lock %d, Non posted %d", + BITS(base, 0, 0xffffff00)<<8, (BITS(lim, 0, 0xffffff00)<<8)+0xffff, + node(lim), link(lim), re(base), we(base), BITS(base, 4, 1), + BITS(base, 7, 1), BITS(lim, 7, 1)); + +} + +void showalldram(int level, struct device *dev) +{ + u8 reg; + for(reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev,reg+4); + showdram(level, reg, base, lim); + } +} + +void showallmmio(int level, struct device *dev) +{ + u8 reg; + for(reg = MMIO_ROUTE_END; reg <= MMIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev,reg+4); + showdram(level, reg, base, lim); + } +} + +void showallpciio(int level, struct device *dev) +{ + u8 reg; + for(reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) { + u32 base = pci_read_config32(dev, reg); + u32 lim = pci_read_config32(dev,reg+4); + showdram(level, reg, base, lim); + } +} + +void showallconfig(int level, struct device *dev) +{ + u8 reg; + for(reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) { + u32 val = pci_read_config32(dev, reg); + showconfig(level, reg, val); + } +} + +void showallroutes(int level, struct device *dev) +{ + showalldram(level, dev); + showallmmio(level, dev); + showallpciio(level, dev); + showallconfig(level, dev); +} Index: northbridge/amd/k8/Makefile =================================================================== --- northbridge/amd/k8/Makefile (revision 937) +++ northbridge/amd/k8/Makefile (working copy) @@ -26,6 +26,7 @@ $(src)/northbridge/amd/k8/common.c \ $(src)/northbridge/amd/k8/cpu.c \ $(src)/northbridge/amd/k8/domain.c \ - $(src)/northbridge/amd/k8/pci.c + $(src)/northbridge/amd/k8/pci.c \ + $(src)/northbridge/amd/k8/util.c endif