On Mon, Oct 20, 2008 at 9:23 PM, ron minnich <[EMAIL PROTECTED]> wrote:
> This code is now callable from anywhere. Here is output. This call is
> from initram. It looks like the dumper code or the routes are wrong in
> some, not all, cases. I am gone for next week on travel so
> I wanted to give people a look at it.
Thanks.
TODO: mv mainboard.c to stage2.c
> mv util.c to dumproutes.c
>
This patch cleans up the showallroutes utility:
1. fix if->in in comments
2. change width of output for different types
3. make all masks 0x so that it's easy to tell a mask
It also changes the invocations to do function 1 instead of 0.
I think we should consider a name that makes it clear that this is only good
for AMD K8+ processors function 1. We might need a similar utility for
other
functions later.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
>
> DRAM(40)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
> DRAM(48)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
> DRAM(50)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
> DRAM(58)01000000-00ffffff, ->(1), R, W, 2 nodes, 1
> DRAM(60)00000000-00ffffff, ->(4), , , No interleave, 0
> DRAM(68)00000000-00ffffff, ->(0), R, W, 8 nodes, 0
> DRAM(70)00000000-00ffffff, ->(0), , , No interleave, 0
> DRAM(78)00000000-00ffffff, ->(0), , , No interleave, 0
> MMIO(80)01a00000-1100ffff, ->(0,2), , , CPU disable 0, Lock 0, Non posted 0
> MMIO(88)75060000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non posted 0
> MMIO(90)51040000-3f00ffff, ->(0,0), , , CPU disable 1, Lock 0, Non posted 0
> MMIO(98)00000000-0000ffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non posted
> 0
> MMIO(a0)01c00000-1100ffff, ->(0,1), , , CPU disable 0, Lock 0, Non posted 1
> MMIO(a8)75000000-0000ffff, ->(2,0), , , CPU disable 0, Lock 0, Non posted 0
> MMIO(b0)51040000-0000ffff, ->(0,0), , , CPU disable 1, Lock 0, Non posted 0
> MMIO(b8)00000000-0000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non posted 0
> PCIIO(c0)00001010-00003110, ->(0,1), , ,VGA 0 ISA 0
> PCIIO(c8)00000750-00000000, ->(2,0), , ,VGA 0 ISA 1
> PCIIO(d0)00002510-00000000, ->(0,0), , ,VGA 1 ISA 0
> PCIIO(d8)00000000-00000000, ->(0,0), , ,VGA 0 ISA 0
> CONFIG(e0)00000000-00000000 ->(0,0), CE 0
> CONFIG(e4)00000000-00000000 ->(0,0), CE 0
> CONFIG(e8)00000000-00000000 ->(0,0), CE 0
> CONFIG(ec)00000000-00000000 ->(0,0), CE 0
Output with patch:
DRAM(40)0000000000-000fffffff, ->(0), R, W, No interleave, 0
DRAM(48)0000000000-0000ffffff, ->(1), , , No interleave, 0
DRAM(50)0000000000-0000ffffff, ->(2), , , No interleave, 0
DRAM(58)0000000000-0000ffffff, ->(3), , , No interleave, 0
DRAM(60)0000000000-0000ffffff, ->(4), , , No interleave, 0
DRAM(68)0000000000-0000ffffff, ->(5), , , No interleave, 0
DRAM(70)0000000000-0000ffffff, ->(6), , , No interleave, 0
DRAM(78)0000000000-0000ffffff, ->(7), , , No interleave, 0
MMIO(80)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(88)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(90)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(98)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(a0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(a8)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(b0)0000000000-000000ffff, ->(0,0), , , CPU disable 0, Lock 0, Non
posted 0
MMIO(b8)00fc000000-00ffffffff, ->(0,0), R, W, CPU disable 0, Lock 0, Non
posted 0
PCIIO(c0)0000000-1ffffff, ->(0,0), R, W,VGA 0 ISA 0
PCIIO(c8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0
PCIIO(d0)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0
PCIIO(d8)0000000-0000fff, ->(0,0), , ,VGA 0 ISA 0
CONFIG(e0)3f-00 ->(0,0),R W CE 0
CONFIG(e4)00-00 ->(0,0), CE 0
CONFIG(e8)00-00 ->(0,0), CE 0
CONFIG(ec)00-00 ->(0,0), CE 0
Thanks,
Myles
Index: mainboard/amd/serengeti/mainboard.c
===================================================================
--- mainboard/amd/serengeti/mainboard.c (revision 941)
+++ mainboard/amd/serengeti/mainboard.c (working copy)
@@ -35,14 +35,14 @@
static void show(struct device *dev)
{
- showallroutes(BIOS_DEBUG, PCI_BDF(0,0x18, 0));
+ showallroutes(BIOS_DEBUG, PCI_BDF(0,0x18, 1));
}
struct device_operations serengeti = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
- .device = 1}}},
- .constructor = default_device_constructor,
+ .device = 1}}},
+ .constructor = default_device_constructor,
.phase6_init = show,
};
Index: mainboard/amd/serengeti/initram.c
===================================================================
--- mainboard/amd/serengeti/initram.c (revision 941)
+++ mainboard/amd/serengeti/initram.c (working copy)
@@ -250,7 +250,7 @@
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
- showallroutes(BIOS_DEBUG, PCI_BDF(0,0x18, 0));
+ showallroutes(BIOS_DEBUG, PCI_BDF(0,0x18, 1));
printk(BIOS_DEBUG, "stage1 returns\n");
return 0;
Index: northbridge/amd/k8/util.c
===================================================================
--- northbridge/amd/k8/util.c (revision 941)
+++ northbridge/amd/k8/util.c (working copy)
@@ -79,7 +79,7 @@
*/
static int node(u32 reg)
{
- return BITS(reg, 0, 7);
+ return BITS(reg, 0, 0x7);
}
/**
@@ -88,7 +88,7 @@
*/
static int link(u32 reg)
{
- return BITS(reg, 4, 3);
+ return BITS(reg, 4, 0x3);
}
@@ -103,9 +103,9 @@
*/
void showdram(int level, u8 which, u32 base, u32 lim)
{
- printk(level, "DRAM(%02x)%08x-%08x, ->(%d), %s, %s, %s, %d\n",
- which, ((base&0xfff0000)<<8),
- ((lim&0xffff0000<<8))+0xffffff,
+ printk(level, "DRAM(%02x)%010llx-%010llx, ->(%d), %s, %s, %s, %d\n",
+ which, (((u64)base&0xffff0000)<<8),
+ (((u64)lim&0xffff0000)<<8)+0xffffff,
node(lim), re(base), we(base),
ileave(base), (lim>>8)&3);
}
@@ -121,10 +121,10 @@
void showconfig(int level, u8 which, u32 reg)
{
/* don't use node() and link() here */
- printk(level, "CONFIG(%02x)%08x-%08x ->(%d,%d),%s %s CE %d\n",
+ printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s CE %d\n",
which, BITS(reg, 24, 0xff), BITS(reg, 16, 0xff),
- BITS(reg, 4, 7), BITS(reg, 8, 3),
- re(reg), we(reg), BITS(reg, 0, 4));
+ BITS(reg, 4, 0x7), BITS(reg, 8, 0x3),
+ re(reg), we(reg), BITS(reg, 2, 0x1));
}
/**
@@ -138,15 +138,16 @@
*/
void showpciio(int level, u8 which, u32 base, u32 lim)
{
- printk(level, "PCIIO(%02x)%08x-%08x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
- which, BITS(base, 12, 0x3fff), BITS(lim, 12, 0x3fff),
+ printk(level, "PCIIO(%02x)%07x-%07x, ->(%d,%d), %s, %s,VGA %d ISA %d\n",
+ which, BITS(base, 12, 0x3fff)<<12,
+ (BITS(lim, 12, 0x3fff)<<12) + 0xfff,
node(lim), link(lim),
re(base), we(base),
- BITS(base, 4, 1), BITS(base, 5, 1));
+ BITS(base, 4, 0x1), BITS(base, 5, 0x1));
}
/**
- * Print the pciio routing info for one base/limit pair.
+ * Print the mmio routing info for one base/limit pair.
* Show base, limit, dest node, dest link on that node, read and write enable, and
* CPU Disable, Lock, and Non-posted.
* @param level printing level
@@ -156,19 +157,19 @@
*/
void showmmio(int level, u8 which, u32 base, u32 lim)
{
- printk(level, "MMIO(%02x)%08x-%08x, ->(%d,%d), %s, %s, CPU disable %d, Lock %d, Non posted %d\n",
- which, BITS(base, 0, 0xffffff00)<<8,
- (BITS(lim, 0, 0xffffff00)<<8)+0xffff,
+ printk(level, "MMIO(%02x)%010llx-%010llx, ->(%d,%d), %s, %s, CPU disable %d, Lock %d, Non posted %d\n",
+ which, ((u64)BITS(base, 0, 0xffffff00))<<8,
+ (((u64)BITS(lim, 0, 0xffffff00))<<8)+0xffff,
node(lim), link(lim), re(base), we(base),
- BITS(base, 4, 1),
- BITS(base, 7, 1), BITS(lim, 7, 1));
+ BITS(base, 4, 0x1),
+ BITS(base, 7, 0x1), BITS(lim, 7, 0x1));
}
/**
* Show all dram routing registers. This function is callable at any time.
* @param level The debug level
- * @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
+ * @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
*/
void showalldram(int level, u32 dev)
{
@@ -183,7 +184,7 @@
/**
* Show all mmio routing registers. This function is callable at any time.
* @param level The debug level
- * @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
+ * @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
*/
void showallmmio(int level, u32 dev)
{
@@ -198,7 +199,7 @@
/**
* Show all pciio routing registers. This function is callable at any time.
* @param level The debug level
- * @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
+ * @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
*/
void showallpciio(int level, u32 dev)
{
@@ -213,7 +214,7 @@
/**
* Show all config routing registers. This function is callable at any time.
* @param level The debug level
- * @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
+ * @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
*/
void showallconfig(int level, u32 dev)
{
@@ -227,7 +228,7 @@
/**
* Show all routing registers. This function is callable at any time.
* @param level The debug level
- * @param dev 32-bit number if the standard bus/dev/fn format which is used raw config space
+ * @param dev 32-bit number in the standard bus/dev/fn format which is used raw config space
*/
void showallroutes(int level, u32 dev)
{
--
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