On 23.10.2008 14:56, [EMAIL PROTECTED] wrote:
> Author: oxygene
> Date: 2008-10-23 14:56:34 +0200 (Thu, 23 Oct 2008)
> New Revision: 947
>
> Modified:
> coreboot-v3/northbridge/intel/i440bxemulation/domain
> coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
> Log:
> Read actual memory size in qemu-i386
>
> Signed-Off-By: Patrick Georgi <[EMAIL PROTECTED]>
> Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>
>
Thanks for the patch. IIRC various qemu versions have different bugs in
that area, so I'd appreciate to know on which version the code was tested.
Please fix up the leftover warning message as indicated below.
The qemu mainboard dts needs to be fixed as well.
Regards,
Carl-Daniel
> Modified: coreboot-v3/northbridge/intel/i440bxemulation/domain
> ===================================================================
> --- coreboot-v3/northbridge/intel/i440bxemulation/domain 2008-10-23
> 01:18:30 UTC (rev 946)
> +++ coreboot-v3/northbridge/intel/i440bxemulation/domain 2008-10-23
> 12:56:34 UTC (rev 947)
> @@ -19,6 +19,5 @@
> */
>
> {
> - ramsize = "128";
> device_operations = "i440bx_domain";
> };
>
> Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
> ===================================================================
> --- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-10-23
> 01:18:30 UTC (rev 946)
> +++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-10-23
> 12:56:34 UTC (rev 947)
> @@ -3,6 +3,7 @@
> *
> * Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL
> * Copyright (C) 2007 Ronald G. Minnich <[EMAIL PROTECTED]>
> + * Copyright (C) 2008 Patrick Georgi <[EMAIL PROTECTED]>
> *
> * This program is free software; you can redistribute it and/or modify
> * it under the terms of the GNU General Public License as published by
> @@ -43,19 +44,30 @@
> #include <device/device.h>
> #include <device/pci.h>
> #include <string.h>
> +#include <io.h>
> #include "i440bx.h"
> #include <statictree.h>
>
> /* Here are the ops for 440BX as a PCI domain. */
>
> +static int inb_cmos(int port)
> +{
> + outb(port, 0x70);
> + return inb(0x71);
> +}
> +
> static void pci_domain_set_resources(struct device *dev)
> {
> struct device *mc_dev;
> u32 tolmk; /* Top of low mem, Kbytes. */
> int idx;
> - struct northbridge_intel_i440bxemulation_domain_config
> *device_configuration =
> - dev->device_configuration;
> - tolmk = device_configuration->ramsize * 1024;
> + /* read large mem memory descriptor
> + for <16 MB read the more detailed small mem descriptor
> + all values in kbytes */
> + tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64;
> + if (tolmk <= 16 * 1024) {
> + tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30);
> + }
> printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts "
> "settings of %d kB instead.\n", tolmk);
>
This printk referred to the old code and it now is wrong.
> mc_dev = dev->link[0].children;
>
>
> --
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> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
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