Was the following a revelation only to me or is it a generally obscure knowledge?
PIIX4 documentation says that bit 2 of PCI config register 0xCB (of function 0) enables access to CMOS memory bank2 via IO ports 0x72 and 0x73 similarly to regular CMOS memory access via 0x70/0x71. I tested this on my 440BX-based system and this does indeed work: $ od -t xC extcmos.img 0000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff * 0000040 aa 04 ff ff ff ff ff 83 06 ff ff ff ff ff ff ff 0000060 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff * 0000200 Most registers are 0xff, but several contain some data, e.g. "83 06" seems to be 0x683, ID of my Pentium III CPU. When bit 2 of 0xCB is zero, then 0x72/0x73 ports seem to provide access to regular CMOS just like 0x70/0x71. -- Andriy Gapon -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
