Author: myles
Date: 2008-10-24 19:53:03 +0200 (Fri, 24 Oct 2008)
New Revision: 952
Modified:
coreboot-v3/northbridge/amd/k8/common.c
coreboot-v3/northbridge/amd/k8/domain.c
Log:
This patch fixes whitespace so that my next patch is easier to read.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTECTED]>
Thanks,
Myles
Modified: coreboot-v3/northbridge/amd/k8/common.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/common.c 2008-10-23 18:55:01 UTC (rev
951)
+++ coreboot-v3/northbridge/amd/k8/common.c 2008-10-24 17:53:03 UTC (rev
952)
@@ -76,6 +76,7 @@
}
}
#endif
+
void get_fx_devs(void)
{
int i;
@@ -123,48 +124,48 @@
struct hw_mem_hole_info mem_hole;
int i;
- mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
- for (i = 0; i < 8; i++) {
- u32 base;
- u32 hole;
- base = f1_read_config32(0x40 + (i << 3));
- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
- continue;
- }
+ for (i = 0; i < 8; i++) {
+ u32 base;
+ u32 hole;
+ base = f1_read_config32(0x40 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
- hole = pci_read_config32(__f1_dev[i], 0xf0);
- if(hole & 1) { // we find the hole
- mem_hole.hole_startk = (hole & (0xff<<24)) >>
10;
- mem_hole.node_id = i; // record the node No
with hole
- break; // only one hole
+ hole = pci_read_config32(__f1_dev[i], 0xf0);
+ if(hole & 1) { // we find the hole
+ mem_hole.hole_startk = (hole & (0xff<<24)) >>
10;
+ mem_hole.node_id = i; // record the node No
with hole
+ break; // only one hole
}
- }
+ }
- //We need to double check if there is speical set on base reg
and limit reg are not continous instead of hole, it will find out it's
hole_startk
- if(mem_hole.node_id==-1) {
- u32 limitk_pri = 0;
- for(i=0; i<8; i++) {
- u32 base, limit;
- unsigned base_k, limit_k;
- base = f1_read_config32(0x40 + (i << 3));
- if ((base & ((1<<1)|(1<<0))) !=
((1<<1)|(1<<0))) {
- continue;
- }
+ //We need to double check if there is speical set on base reg
and limit reg are not continous instead of hole, it will find out it's
hole_startk
+ if(mem_hole.node_id==-1) {
+ u32 limitk_pri = 0;
+ for(i=0; i<8; i++) {
+ u32 base, limit;
+ unsigned base_k, limit_k;
+ base = f1_read_config32(0x40 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) !=
((1<<1)|(1<<0))) {
+ continue;
+ }
- base_k = (base & 0xffff0000) >> 2;
- if(limitk_pri != base_k) { // we find the hole
- mem_hole.hole_startk = limitk_pri;
- mem_hole.node_id = i;
- break; //only one hole
+ base_k = (base & 0xffff0000) >> 2;
+ if(limitk_pri != base_k) { // we find the hole
+ mem_hole.hole_startk = limitk_pri;
+ mem_hole.node_id = i;
+ break; //only one hole
}
- limit = f1_read_config32(0x44 + (i << 3));
- limit_k = ((limit + 0x00010000) & 0xffff0000)
>> 2;
- limitk_pri = limit_k;
- }
- }
+ limit = f1_read_config32(0x44 + (i << 3));
+ limit_k = ((limit + 0x00010000) & 0xffff0000)
>> 2;
+ limitk_pri = limit_k;
+ }
+ }
return mem_hole;
@@ -172,35 +173,35 @@
void disable_hoist_memory(unsigned long hole_startk, int i)
{
- int ii;
- struct device * dev;
- u32 base, limit;
- u32 hoist;
+ int ii;
+ struct device * dev;
+ u32 base, limit;
+ u32 hoist;
u32 hole_sizek;
- //1. find which node has hole
- //2. change limit in that node.
- //3. change base and limit in later node
- //4. clear that node f0
+ //1. find which node has hole
+ //2. change limit in that node.
+ //3. change base and limit in later node
+ //4. clear that node f0
//if there is not mem hole enabled, we need to change it's base instead
hole_sizek = (4*1024*1024) - hole_startk;
- for(ii=7;ii>i;ii--) {
+ for(ii=7;ii>i;ii--) {
- base = f1_read_config32(0x40 + (ii << 3));
- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
- continue;
- }
+ base = f1_read_config32(0x40 + (ii << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
limit = f1_read_config32(0x44 + (ii << 3));
- f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
- f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
- }
- limit = f1_read_config32(0x44 + (i << 3));
- f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
- dev = __f1_dev[i];
+ f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
+ f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
+ }
+ limit = f1_read_config32(0x44 + (i << 3));
+ f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
+ dev = __f1_dev[i];
hoist = pci_read_config32(dev, 0xf0);
if(hoist & 1) {
pci_write_config32(dev, 0xf0, 0);
@@ -214,30 +215,30 @@
u32 hoist_memory(unsigned long hole_startk, int i)
{
- int ii;
- u32 carry_over;
- struct device * dev;
- u32 base, limit;
- u32 basek;
- u32 hoist;
+ int ii;
+ u32 carry_over;
+ struct device * dev;
+ u32 base, limit;
+ u32 basek;
+ u32 hoist;
- carry_over = (4*1024*1024) - hole_startk;
+ carry_over = (4*1024*1024) - hole_startk;
- for(ii=7;ii>i;ii--) {
+ for(ii=7;ii>i;ii--) {
- base = f1_read_config32(0x40 + (ii << 3));
- if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
- continue;
- }
+ base = f1_read_config32(0x40 + (ii << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
limit = f1_read_config32(0x44 + (ii << 3));
- f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
- f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
- }
- limit = f1_read_config32(0x44 + (i << 3));
- f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
- dev = __f1_dev[i];
- base = pci_read_config32(dev, 0x40 + (i << 3));
- basek = (base & 0xffff0000) >> 2;
+ f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
+ f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
+ }
+ limit = f1_read_config32(0x44 + (i << 3));
+ f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
+ dev = __f1_dev[i];
+ base = pci_read_config32(dev, 0x40 + (i << 3));
+ basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0,
overflow
//so need to change base reg instead, new basek will be
4*1024*1024
@@ -247,17 +248,17 @@
}
else
{
- hoist = /* hole start address */
- ((hole_startk << 10) & 0xff000000) +
- /* hole address to memory controller address */
- (((basek + carry_over) >> 6) & 0x0000ff00) +
- /* enable */
- 1;
+ hoist = /* hole start address */
+ ((hole_startk << 10) & 0xff000000) +
+ /* hole address to memory controller address */
+ (((basek + carry_over) >> 6) & 0x0000ff00) +
+ /* enable */
+ 1;
- pci_write_config32(dev, 0xf0, hoist);
+ pci_write_config32(dev, 0xf0, hoist);
}
- return carry_over;
+ return carry_over;
}
#endif
Modified: coreboot-v3/northbridge/amd/k8/domain.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/domain.c 2008-10-23 18:55:01 UTC (rev
951)
+++ coreboot-v3/northbridge/amd/k8/domain.c 2008-10-24 17:53:03 UTC (rev
952)
@@ -126,18 +126,18 @@
}
}
#ifndef CONFIG_PCI_64BIT_PREF_MEM
- /* Initialize the system wide io space constraints */
+ /* Initialize the system-wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
- /* Initialize the system wide memory resources constraints */
+ /* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
#else
- /* Initialize the system wide io space constraints */
+ /* Initialize the system-wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
@@ -145,7 +145,7 @@
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
- /* Initialize the system wide prefetchable memory resources constraints
*/
+ /* Initialize the system-wide prefetchable memory resource constraints
*/
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
@@ -153,7 +153,7 @@
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
- /* Initialize the system wide memory resources constraints */
+ /* Initialize the system-wide memory resource constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM;
@@ -197,10 +197,10 @@
mem2 = find_resource(dev, 2);
#if 1
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size:
0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size:
0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align:
%d\n",
+ mem1->base, mem1->limit, mem1->size, mem1->align);
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align:
%d\n",
+ mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
/* See if both resources have roughly the same limits */
@@ -227,10 +227,10 @@
}
#if 1
- printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size:
0x%08Lx align: %d\n",
- mem1->base, mem1->limit, mem1->size, mem1->align);
- printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size:
0x%08Lx align: %d\n",
- mem2->base, mem2->limit, mem2->size, mem2->align);
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align:
%d\n",
+ mem1->base, mem1->limit, mem1->size, mem1->align);
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align:
%d\n",
+ mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
last = &dev->resource[dev->resources];
@@ -264,10 +264,11 @@
#endif
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
- /* if the hw mem hole is already set in raminit stage, here we will
compare mmio_basek and hole_basek
- * if mmio_basek is bigger that hole_basek and will use hole_basek as
mmio_basek and we don't need to reset hole.
- * otherwise We reset the hole to the mmio_basek
- */
+ /* If the hw mem hole is already set in raminit stage, here we will
+ * compare mmio_basek and hole_basek. If mmio_basek is bigger than
+ * hole_basek, we use hole_basek as mmio_basek and we don't need
+ * to reset hole. Otherwise, we reset the hole to the mmio_basek.
+ */
mem_hole = get_hw_mem_hole_info();
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
