Author: rminnich
Date: 2008-11-01 01:53:01 +0100 (Sat, 01 Nov 2008)
New Revision: 976
Modified:
coreboot-v3/arch/x86/stage1_mtrr.c
coreboot-v3/arch/x86/via/stage1.c
coreboot-v3/mainboard/via/epia-cn/Makefile
coreboot-v3/mainboard/via/epia-cn/stage1.c
Log:
Get via to use standard mtrr init functions. Start to document them.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/stage1_mtrr.c
===================================================================
--- coreboot-v3/arch/x86/stage1_mtrr.c 2008-10-31 22:43:02 UTC (rev 975)
+++ coreboot-v3/arch/x86/stage1_mtrr.c 2008-11-01 00:53:01 UTC (rev 976)
@@ -106,6 +106,10 @@
}
+/**
+ * Call this function early in stage1 to enable mtrrs, which will ensure
+ * caching of ROM
+ */
void early_mtrr_init(void)
{
static const unsigned long mtrr_msrs[] = {
Modified: coreboot-v3/arch/x86/via/stage1.c
===================================================================
--- coreboot-v3/arch/x86/via/stage1.c 2008-10-31 22:43:02 UTC (rev 975)
+++ coreboot-v3/arch/x86/via/stage1.c 2008-11-01 00:53:01 UTC (rev 976)
@@ -30,22 +30,7 @@
#include <mtrr.h>
#include <via_c7.h>
-#ifdef NO_IDEA_WHETHER_THIS_IS_RELEVANT_ON_C7
/**
- * Set the MTRR for initial ram access.
- * be warned, this will be used by core other than core 0/node 0 or
core0/node0 when cpu_reset.
- * This warning has some significance I don't yet understand.
- */
-void set_init_ram_access(void)
-{
- set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
-}
-#endif
-
-#define __stringify_1(x) #x
-#define __stringify(x) __stringify_1(x)
-
-/**
* Disable Cache As RAM (CAR) after memory is setup.
*/
void disable_car(void)
Modified: coreboot-v3/mainboard/via/epia-cn/Makefile
===================================================================
--- coreboot-v3/mainboard/via/epia-cn/Makefile 2008-10-31 22:43:02 UTC (rev
975)
+++ coreboot-v3/mainboard/via/epia-cn/Makefile 2008-11-01 00:53:01 UTC (rev
976)
@@ -18,7 +18,9 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
+STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
+ $(src)/arch/x86/stage1_mtrr.c \
+ $(src)/mainboard/$(MAINBOARDDIR)/stage1.c
INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/via/cn700/initram.c \
Modified: coreboot-v3/mainboard/via/epia-cn/stage1.c
===================================================================
--- coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-10-31 22:43:02 UTC (rev
975)
+++ coreboot-v3/mainboard/via/epia-cn/stage1.c 2008-11-01 00:53:01 UTC (rev
976)
@@ -36,10 +36,15 @@
void hardware_stage1(void)
{
+ void early_mtrr_init(void);
void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase);
u32 dev;
post_code(POST_START_OF_MAIN);
+
+ /* do this or watch the system run slowly */
+ early_mtrr_init();
+
vt1211_enable_serial(0x2e, 2, 0x3f8);
/* Enable multifunction for northbridge. */
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
