AMD K8 processors claim that they're using HyperTransport 1.02, but the
publicly available documentation (specifically the BKDG) states that the
HT version is 1.03 in reality.
lspci will issue a warning "!!! Possibly incomplete decoding" and only
decode some basic HT properties for HT versions before 1.03.
Move that boundary down to HT version 1.02.
Example output before the patch:
00:18.0 0600: 1022:1100
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Capabilities: [80] HyperTransport: Host or Secondary Interface
!!! Possibly incomplete decoding
Command: WarmRst+ DblEnd-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0
Link Config: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit
Revision ID: 1.02
Example output with the same processor after the patch:
00:18.0 0600: 1022:1100
Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Capabilities: [80] HyperTransport: Host or Secondary Interface
Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave-
<EOCErr- DUL-
Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO-
<CRCErr=0 IsocEn- LSEn- ExtCTL- 64b-
Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit
DwFcInEn- LWO=16bit DwFcOutEn-
Revision ID: 1.02
Link Frequency: 1.0GHz
Link Error: <Prot- <Ovfl- <EOC- CTLTm-
Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz-
600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend-
Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD-
ExtRS- UCnfE-
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
--
http://www.hailfinger.org/
From 3ec82ad313d0172227916c95b50a2c2f847fa4b7 Mon Sep 17 00:00:00 2001
From: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Date: Tue, 4 Nov 2008 00:52:32 +0100
Subject: [PATCH] Decode HyperTransport 1.02 as 1.03
AMD K8 processors claim that they're using HyperTransport 1.02, but the
publicly available documentation (specifically the BKDG) states that
the HT version is 1.03 in reality.
lspci will issue a warning "!!! Possibly incomplete decoding" and
only decode some basic HT properties for HT versions before 1.03.
Move that boundary down to HT version 1.02.
---
lspci.c | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/lspci.c b/lspci.c
index 5254b75..c17c4c1 100644
--- a/lspci.c
+++ b/lspci.c
@@ -571,10 +571,10 @@ cap_ht_pri(struct device *d, int where, int cmd)
if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
return;
rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
- if (rid < 0x23 && rid > 0x11)
+ if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c DUL%c\n";
else
fmt = "\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c\n";
@@ -585,7 +585,7 @@ cap_ht_pri(struct device *d, int where, int cmd)
FLAG(cmd, PCI_HT_PRI_CMD_DD),
FLAG(cmd, PCI_HT_PRI_CMD_DUL));
lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
@@ -603,7 +603,7 @@ cap_ht_pri(struct device *d, int where, int cmd)
FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
FLAG(lctr0, PCI_HT_LCTR_64B));
lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config 0: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
@@ -617,7 +617,7 @@ cap_ht_pri(struct device *d, int where, int cmd)
FLAG(lcnf0, PCI_HT_LCNF_DFIE),
FLAG(lcnf0, PCI_HT_LCNF_DFOE));
lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
@@ -635,7 +635,7 @@ cap_ht_pri(struct device *d, int where, int cmd)
FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
FLAG(lctr1, PCI_HT_LCTR_64B));
lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config 1: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
@@ -650,7 +650,7 @@ cap_ht_pri(struct device *d, int where, int cmd)
FLAG(lcnf1, PCI_HT_LCNF_DFOE));
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
- if (rid < 0x23)
+ if (rid < 0x22)
return;
lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
@@ -739,10 +739,10 @@ cap_ht_sec(struct device *d, int where, int cmd)
if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
return;
rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
- if (rid < 0x23 && rid > 0x11)
+ if (rid < 0x22 && rid > 0x11)
printf("\t\t!!! Possibly incomplete decoding\n");
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
else
fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
@@ -756,7 +756,7 @@ cap_ht_sec(struct device *d, int where, int cmd)
FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
FLAG(cmd, PCI_HT_SEC_CMD_DUL));
lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
else
fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
@@ -774,7 +774,7 @@ cap_ht_sec(struct device *d, int where, int cmd)
FLAG(lctr, PCI_HT_LCTR_EXTCTL),
FLAG(lctr, PCI_HT_LCTR_64B));
lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
- if (rid >= 0x23)
+ if (rid >= 0x22)
fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
else
fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
@@ -789,7 +789,7 @@ cap_ht_sec(struct device *d, int where, int cmd)
FLAG(lcnf, PCI_HT_LCNF_DFOE));
printf("\t\tRevision ID: %u.%02u\n",
(rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
- if (rid < 0x23)
+ if (rid < 0x22)
return;
lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
--
1.5.2.4
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
