On 13.11.2008 01:19, Mart Raudsepp wrote: > artecgroup/dbe61: Get DBE61A RAM setup and timing working. > > * Uncomment the dbe61a SPD table > * Modify spd_read_byte to support a DIMM SPD address at DIMM_DBE61A that > outputs data from dbe61a SPD table instead of dbe61c; approach tip from Marc > Jones > * In main() after setting up DBE61C 256MB RAM, run a ram_check, and if that > returns a greater than zero verify error count set up 128MB for DBE61A instead > * Tweak the dbe61a SPD table to result in LX MSR values as known to work in > Artec v2 branch - this is DBE62/DBE61C values, with density and NUM_COLUMNS > halved, and some timings tweaked according to the v2 results. > > Now memtest86+ is quite happy on both DBE61C and DBE61A. > > Note that it should be better to ram_check in the high memory areas, but that > doesn't seem to currently work. > Low memory check seems fine for the immediate time being, as the results > appear shifted there as well with the wrong size/timing setup. > > Signed-off-by: Mart Raudsepp <[EMAIL PROTECTED]> >
Good enough for now. Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
