Index: arch/x86/Makefile Add core2 stage1.c dependency Index: arch/x86/intel/core2/stage1.c Initial core2 disable_car and stop_ap disable_car is wrong but we can fix that tomorrow -- it's core 2 day on friday! Index: arch/x86/via/stage1.c Add empty stop_ap() Index: mainboard/kontron/986lcd-m/stage1_debug.c Cleanup Index: mainboard/kontron/986lcd-m/initram.c Cleanup Index: mainboard/jetway/j7f2/stage1.c Remove definition of stop_ap; this belongs in the cpu! Index: southbridge/intel/i82801gx/libsmbus.c Fix definition of TIMEOUT (i.e. remove it) Signed-off-by: Ronald G. Minnich Index: southbridge/intel/i82801gx/libsmbus.c =================================================================== --- southbridge/intel/i82801gx/libsmbus.c (revision 1018) +++ southbridge/intel/i82801gx/libsmbus.c (working copy) @@ -32,8 +32,8 @@ #include "i82801gx.h" /* this is very chipset-specific. */ -#define SMBUS_TIMEOUT (100*1000*10) /* These are common functions used in stage 1 and stage2 */ +#warning why do we have an smbus_delay here void smbus_delay(void) { inb(0x80); Index: mainboard/jetway/j7f2/stage1.c =================================================================== --- mainboard/jetway/j7f2/stage1.c (revision 1018) +++ mainboard/jetway/j7f2/stage1.c (working copy) @@ -28,12 +28,6 @@ #include #include -/* Placeholders, build fails without them */ -void stop_ap(void) -{ - //int noop; -} - void hardware_stage1(void) { u32 dev; Index: mainboard/kontron/986lcd-m/initram.c =================================================================== --- mainboard/kontron/986lcd-m/initram.c (revision 1018) +++ mainboard/kontron/986lcd-m/initram.c (working copy) @@ -33,7 +33,6 @@ #include #include #include -#include #include #include Index: mainboard/kontron/986lcd-m/stage1_debug.c =================================================================== --- mainboard/kontron/986lcd-m/stage1_debug.c (revision 1018) +++ mainboard/kontron/986lcd-m/stage1_debug.c (working copy) @@ -25,7 +25,6 @@ #include #include #include -#include #include #define SMBUS_MEM_DEVICE_START 0x50 Index: arch/x86/via/stage1.c =================================================================== --- arch/x86/via/stage1.c (revision 1018) +++ arch/x86/via/stage1.c (working copy) @@ -90,3 +90,8 @@ [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) : "memory"); } + +void stop_ap(void) +{ +} + Index: arch/x86/intel/core2/stage1.c =================================================================== --- arch/x86/intel/core2/stage1.c (revision 0) +++ arch/x86/intel/core2/stage1.c (revision 0) @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Carl-Daniel Hailfinger + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * Disable Cache As RAM (CAR) after memory is setup. + */ +void disable_car(void) +{ + printk(BIOS_DEBUG, "disable_car entry\n"); + /* Determine new global variable location. Stack organization from top + * Top 4 bytes are reserved + * Pointer to global variables + * Global variables + * + * Align the result to 8 bytes + */ + struct global_vars *const newlocation = (struct global_vars *)((RAM_STACK_BASE - sizeof(struct global_vars *) - sizeof(struct global_vars)) & ~0x7); + /* Copy global variables to new location. */ + memcpy(newlocation, global_vars(), sizeof(struct global_vars)); + printk(BIOS_DEBUG, "disable_car global_vars copy done\n"); + /* Set the new global variable pointer. */ + *(struct global_vars **)(RAM_STACK_BASE - sizeof(struct global_vars *)) = newlocation; + + printk(BIOS_DEBUG, "disable_car global_vars pointer adjusted\n"); + printk(BIOS_DEBUG, "entering asm code now\n"); + + __asm__ __volatile__( + " movl %[newesp], %%esp \n" + + /* We don't need cache as ram for now on */ + /* disable cache */ + " movl %%cr0, %%eax \n" + " orl $(0x1<<30),%%eax \n" + " movl %%eax, %%cr0 \n" + + /* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/ + /* clear sth */ + " xorl %%eax, %%eax \n" + " xorl %%edx, %%edx \n" + " movl $0x201, %%ecx \n" + " wrmsr \n" + " movl $0x200, %%ecx \n" + " wrmsr \n" + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + " movl %[_MTRRdefType_MSR], %%ecx \n" + " xorl %%edx, %%edx \n" + /* Enable Variable and Disable Fixed MTRRs */ + " movl $0x00000800, %%eax \n" + " wrmsr \n" + + /* enable cache */ + " movl %%cr0, %%eax \n" + " andl $0x9fffffff,%%eax \n" + " movl %%eax, %%cr0 \n" + + " wbinvd \n" + + " call stage1_phase3 \n" + :: [newesp] "i" (newlocation), + [_MTRRdefType_MSR] "i" (MTRRdefType_MSR) + : "memory"); +} + +void stop_ap(void) +{ +} + Index: arch/x86/Makefile =================================================================== --- arch/x86/Makefile (revision 1018) +++ arch/x86/Makefile (working copy) @@ -125,7 +125,7 @@ else ifeq ($(CONFIG_CPU_INTEL_CORE2),y) STAGE0_CAR_OBJ = intel/core2/stage0.o - #STAGE0_ARCH_X86_SRC += intel/core2/stage1.c + STAGE0_ARCH_X86_SRC += intel/core2/stage1.c else ifeq ($(CONFIG_CPU_VIA_C7),y) STAGE0_CAR_OBJ = via/stage0.o