Index: northbridge/intel/i945/stage1.c Make statics non-static (we don't do buildrom any more) Index: northbridge/intel/i945/raminit.c remove snarf-o that left k8 in (I used wrong script I guess?) Index: southbridge/intel/i82801gx/libsmbus.c Corrections (minor) Index: southbridge/intel/i82801gx/stage1_smbus.c static to global Index: mainboard/kontron/986lcd-m/stage1_debug.c don't include statictree.c Index: mainboard/kontron/986lcd-m/stage1.c Remove functions that have to be in initram. Index: mainboard/kontron/986lcd-m/initram.c Add functions. This is all about splitting auto.c into stage1 and initram. stage1 is very small and limited. Signed-off-by: Ronald G. Minnich Index: mainboard/kontron/986lcd-m/initram.c =================================================================== --- mainboard/kontron/986lcd-m/initram.c (revision 1018) +++ mainboard/kontron/986lcd-m/initram.c (working copy) @@ -33,7 +33,6 @@ #include #include #include -#include #include #include @@ -73,6 +72,92 @@ return do_smbus_read_byte(device, address); } +static void early_ich7_init(void) +{ + u8 reg8; + u32 reg32; + + // program secondary mlt XXX byte? + pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x3241; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3210; + RCBA16(0x3148) = 0x3210; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Disable unused devices */ + RCBA32(0x3418) = 0x000e0063; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + + + /** * main for initram for the AMD DBM690T * @param init_detected Used to indicate that we have been started via init @@ -89,6 +174,11 @@ */ int main(void) { + void i945_early_initialization(void); + void enable_smbus(void); + int fixup_i945_errata(void); + void i945_late_initialization(void); + if (MCHBAR16(SSKPD) == 0xCAFE) { printk(BIOS_DEBUG, "soft reset detected.\n"); boot_mode = 1; @@ -102,7 +192,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if DEFAULT_CONSOLE_LOGLEVEL > 8 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 dump_spd_registers(); #endif Index: mainboard/kontron/986lcd-m/stage1.c =================================================================== --- mainboard/kontron/986lcd-m/stage1.c (revision 1018) +++ mainboard/kontron/986lcd-m/stage1.c (working copy) @@ -203,90 +203,6 @@ rawpnp_exit_ext_func_mode(port); } -static void rcba_config(void) -{ - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; - - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x3241; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3210; - RCBA16(0x3148) = 0x3210; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - - /* Disable unused devices */ - RCBA32(0x3418) = 0x000e0063; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; -} - -static void early_ich7_init(void) -{ - u8 reg8; - u32 reg32; - - // program secondary mlt XXX byte? - pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} void hardware_stage1(void) { void early_superio_config_w83627thg(void); Index: mainboard/kontron/986lcd-m/stage1_debug.c =================================================================== --- mainboard/kontron/986lcd-m/stage1_debug.c (revision 1018) +++ mainboard/kontron/986lcd-m/stage1_debug.c (working copy) @@ -25,7 +25,6 @@ #include #include #include -#include #include #define SMBUS_MEM_DEVICE_START 0x50 Index: southbridge/intel/i82801gx/stage1_smbus.c =================================================================== --- southbridge/intel/i82801gx/stage1_smbus.c (revision 1018) +++ southbridge/intel/i82801gx/stage1_smbus.c (working copy) @@ -30,7 +30,7 @@ #include #include "i82801gx.h" -static void enable_smbus(void) +void enable_smbus(void) { u32 dev; Index: southbridge/intel/i82801gx/libsmbus.c =================================================================== --- southbridge/intel/i82801gx/libsmbus.c (revision 1018) +++ southbridge/intel/i82801gx/libsmbus.c (working copy) @@ -32,8 +32,8 @@ #include "i82801gx.h" /* this is very chipset-specific. */ -#define SMBUS_TIMEOUT (100*1000*10) /* These are common functions used in stage 1 and stage2 */ +#warning why do we have an smbus_delay here void smbus_delay(void) { inb(0x80); Index: northbridge/intel/i945/raminit.c =================================================================== --- northbridge/intel/i945/raminit.c (revision 1018) +++ northbridge/intel/i945/raminit.c (working copy) @@ -26,8 +26,6 @@ #include #include #include -#include -#include #include #include #include Index: northbridge/intel/i945/stage1.c =================================================================== --- northbridge/intel/i945/stage1.c (revision 1018) +++ northbridge/intel/i945/stage1.c (working copy) @@ -550,7 +550,7 @@ pci_conf1_write_config32(PCI_BDF(0, 0x1c, 0), 0xd8, 0x00110000); } -static void i945_early_initialization(void) +void i945_early_initialization(void) { /* Print some chipset specific information */ i945_detect_chipset(); @@ -562,7 +562,7 @@ RCBA32(GCS) &= (~0x04); } -static void i945_late_initialization(void) +void i945_late_initialization(void) { i945_setup_egress_port();