Author: rminnich
Date: 2008-11-14 17:21:21 +0100 (Fri, 14 Nov 2008)
New Revision: 1025
Modified:
coreboot-v3/mainboard/kontron/986lcd-m/initram.c
coreboot-v3/northbridge/intel/i945/northbridge.c
coreboot-v3/southbridge/intel/i82801gx/smbus.c
Log:
Get rid of un-needed functions in initram.c
Comment out not-yet-supplied initialize_cpus.
Fix missing ; in smbus.c
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/mainboard/kontron/986lcd-m/initram.c
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-11-14 16:15:33 UTC
(rev 1024)
+++ coreboot-v3/mainboard/kontron/986lcd-m/initram.c 2008-11-14 16:21:21 UTC
(rev 1025)
@@ -43,26 +43,7 @@
#define DIMM0 0x50
#define DIMM1 0x51
-/* this code is very mainboard dependent, sadly. */
/**
- * no op at present
- */
-static void memreset_setup(void)
-{
-}
-
-/**
- * this is a no op on this platform.
- */
-void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-/**
* read a byte from spd.
* @param device device to read from
* @param address address in the spd ROM
Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-14 16:15:33 UTC
(rev 1024)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-14 16:21:21 UTC
(rev 1025)
@@ -209,7 +209,8 @@
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
- printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR
0x%08lx-0x%08llx.\n",
+
+ printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR
0x%08lx-0x%08lx.\n",
(u64) resource->base, (u64) (resource->base +
resource->size));
}
@@ -250,10 +251,12 @@
.ops_pci = &intel_pci_ops,
};
-
+#warning need to write initialize_cpus
static void cpu_bus_init(struct device * dev)
{
+ /* what to do here?
initialize_cpus(&dev->link[0]);
+ */
}
static void cpu_bus_noop(struct device * dev)
Modified: coreboot-v3/southbridge/intel/i82801gx/smbus.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/smbus.c 2008-11-14 16:15:33 UTC
(rev 1024)
+++ coreboot-v3/southbridge/intel/i82801gx/smbus.c 2008-11-14 16:21:21 UTC
(rev 1025)
@@ -45,7 +45,7 @@
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = smbus_read_byte,
};
-void i82801gx_enable(struct device * dev)
+void i82801gx_enable(struct device * dev);
/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
struct device_operations i82801gx_smbus = {
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
