Author: hailfinger
Date: 2008-11-16 02:52:08 +0100 (Sun, 16 Nov 2008)
New Revision: 1032
Modified:
coreboot-v3/superio/winbond/w83627thg/stage1.c
coreboot-v3/superio/winbond/w83627thg/superio.c
Log:
Drop duplicated functions from W83627THG SuperI/O stage1 code and fix
up a function prototype.
Fix up #include statements for W83627THG SuperI/O stage2 code.
Use anonymous instead of named unions in struct device.
Point pnp_dev_info members to w83627thg_ops.
Disable UART and keyboard initialization for now.
Add new code in phase3_chip_setup_dev to fill in configuration values
from the dts (code is partially disabled).
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/superio/winbond/w83627thg/stage1.c
===================================================================
--- coreboot-v3/superio/winbond/w83627thg/stage1.c 2008-11-16 01:22:18 UTC
(rev 1031)
+++ coreboot-v3/superio/winbond/w83627thg/stage1.c 2008-11-16 01:52:08 UTC
(rev 1032)
@@ -21,25 +21,12 @@
#include <device/pnp.h>
#include "w83627thg.h"
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static void w83627thg_enable_serial(u8 dev, u8 serial, u16 iobase)
{
- unsigned int port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
+ rawpnp_enter_ext_func_mode(dev);
+ rawpnp_set_logical_device(dev, serial);
+ rawpnp_set_enable(dev, 0);
+ rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ rawpnp_set_enable(dev, 1);
+ rawpnp_exit_ext_func_mode(dev);
}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- unsigned int port = dev >> 8;
- outb(0xaa, port);
-}
-
-static void w83627thg_enable_serial(device_t dev, unsigned int iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
Modified: coreboot-v3/superio/winbond/w83627thg/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627thg/superio.c 2008-11-16 01:22:18 UTC
(rev 1031)
+++ coreboot-v3/superio/winbond/w83627thg/superio.c 2008-11-16 01:52:08 UTC
(rev 1032)
@@ -30,16 +30,16 @@
#include <keyboard.h>
// #include <pc80/mc146818rtc.h>
#include <statictree.h>
-#include "w83627hf.h"
+#include "w83627thg.h"
static void w83627thg_enter_ext_func_mode(struct device * dev)
{
- outb(0x87, dev->path.u.pnp.port);
- outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.pnp.port);
+ outb(0x87, dev->path.pnp.port);
}
static void w83627thg_exit_ext_func_mode(struct device * dev)
{
- outb(0xaa, dev->path.u.pnp.port);
+ outb(0xaa, dev->path.pnp.port);
}
static void w83627thg_init(struct device * dev)
@@ -53,19 +53,19 @@
return;
}
conf = dev->device_configuration;
- switch(dev->path.u.pnp.device) {
+ switch(dev->path.pnp.device) {
case W83627THG_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
- init_uart8250(res0->base, &conf->com1);
+// init_uart8250(res0->base, &conf->com1);
break;
case W83627THG_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
- init_uart8250(res0->base, &conf->com2);
+// init_uart8250(res0->base, &conf->com2);
break;
case W83627THG_KBC:
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
- init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+// init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
}
}
@@ -92,31 +92,98 @@
}
static void phase3_chip_setup_dev(struct device *dev);
-static struct device_operations w83627thg_ops = {
+struct device_operations w83627thg_ops = {
.phase3_chip_setup_dev = phase3_chip_setup_dev,
.phase3_enable = w83627thg_enable,
.phase4_read_resources = pnp_read_resources,
.phase4_set_resources = w83627thg_set_resources,
.phase5_enable_resources = w83627thg_enable_resources,
- .enable = ,
- .init = w83627thg_init,
+ .phase6_init = w83627thg_init,
};
+/* TODO: this device is not at all filled out. Just copied from v2. */
static struct pnp_info pnp_dev_info[] = {
- { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &w83627thg_ops, W83627THG_FDC, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {
0x07f8, 0}, },
+ { &w83627thg_ops, W83627THG_PP, 0, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {
0x07f8, 0}, },
+ { &w83627thg_ops, W83627THG_SP1, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 },
},
+ { &w83627thg_ops, W83627THG_SP2, 0, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 },
},
// No 4 { 0,},
- { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {
0x7ff, 0 }, { 0x7ff, 0x4}, },
- { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {
0x7ff, 0 }, {0x7fe, 4} },
- { &ops, W83627THG_GPIO2,},
- { &ops, W83627THG_GPIO3,},
- { &ops, W83627THG_ACPI, PNP_IRQ0, },
- { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
+ { &w83627thg_ops, W83627THG_KBC, 0, PNP_IO0 | PNP_IO1 | PNP_IRQ0 |
PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &w83627thg_ops, W83627THG_GAME_MIDI_GPIO1, 0, PNP_IO0 | PNP_IO1 |
PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} },
+ { &w83627thg_ops, W83627THG_GPIO2,},
+ { &w83627thg_ops, W83627THG_GPIO3,},
+ { &w83627thg_ops, W83627THG_ACPI, 0, PNP_IRQ0, },
+ { &w83627thg_ops, W83627THG_HWM, 0, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
};
static void phase3_chip_setup_dev(struct device *dev)
{
+ /* Get dts values and populate pnp_dev_info. */
+ const struct superio_winbond_w83627thg_dts_config * const conf =
dev->device_configuration;
+
+#if 0
+These are not set up at all v2. Ignore for now. */
+ /* Floppy */
+ pnp_dev_info[W83627THG_FDC].enable = conf->floppyenable;
+ pnp_dev_info[W83627THG_FDC].io0.val = conf->floppyio;
+ pnp_dev_info[W83627THG_FDC].irq0.val = conf->floppyirq;
+ pnp_dev_info[W83627THG_FDC].drq0.val = conf->floppydrq;
+
+ /* Parallel port */
+ pnp_dev_info[W83627THG_PP].enable = conf->ppenable;
+ pnp_dev_info[W83627THG_PP].io0.val = conf->ppio;
+ pnp_dev_info[W83627THG_PP].irq0.val = conf->ppirq;
+
+ /* Consumer IR */
+ pnp_dev_info[W83627THG_CIR].enable = conf->cirenable;
+
+ /* Game port */
+ pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].enable = conf->gameenable;
+ pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io0.val = conf->gameio;
+ pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].io1.val = conf->gameio2;
+ pnp_dev_info[W83627THG_GAME_MIDI_GPIO1].irq0.val = conf->gameirq;
+
+ /* GPIO2 */
+ pnp_dev_info[W83627THG_GPIO2].enable = conf->gpio2enable;
+
+ /* GPIO3 */
+ pnp_dev_info[W83627THG_GPIO3].enable = conf->gpio3enable;
+
+ /* ACPI */
+ pnp_dev_info[W83627THG_ACPI].enable = conf->acpienable;
+
+ /* Hardware Monitor */
+ pnp_dev_info[W83627THG_HWM].enable = conf->hwmenable;
+ pnp_dev_info[W83627THG_HWM].io0.val = conf->hwmio;
+ pnp_dev_info[W83627THG_HWM].irq0.val = conf->hwmirq;
+
+#endif
+
+ /* COM1 */
+ pnp_dev_info[W83627THG_SP1].enable = conf->com1enable;
+ pnp_dev_info[W83627THG_SP1].io0.val = conf->com1io;
+ pnp_dev_info[W83627THG_SP1].irq0.val = conf->com1irq;
+
+ /* COM2 */
+ pnp_dev_info[W83627THG_SP2].enable = conf->com2enable;
+ pnp_dev_info[W83627THG_SP2].io0.val = conf->com2io;
+ pnp_dev_info[W83627THG_SP2].irq0.val = conf->com2irq;
+
+ /* Keyboard */
+ pnp_dev_info[W83627THG_KBC].enable = conf->kbenable;
+ pnp_dev_info[W83627THG_KBC].io0.val = conf->kbio;
+ pnp_dev_info[W83627THG_KBC].io1.val = conf->kbio2;
+ pnp_dev_info[W83627THG_KBC].irq0.val = conf->kbirq;
+ pnp_dev_info[W83627THG_KBC].irq1.val = conf->kbirq2;
+
+ /* Initialize SuperIO for PNP children. */
+ if (!dev->links) {
+ dev->links = 1;
+ dev->link[0].dev = dev;
+ dev->link[0].children = NULL;
+ dev->link[0].link = 0;
+ }
+
+ /* Call init with updated tables to create children. */
pnp_enable_devices(dev, &w83627thg_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
--
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