This patch fixes ht chain handling.
include/device/path.h:
Add a ht_path type to hold chain number and UnitID.
include/device/hypertransport.h:
Remove offset_unitid from prototype.
mainboard/amd/serengeti/dts:
Update to use [EMAIL PROTECTED],unitid.
Add 8132 devices.
Add pci_X for devices that would otherwise collide.
Since setting the UnitID for an HT device affects the devfn of all the
PCI devices on the chip, they all start at 0,0 and go from there.
If you look in a data sheet it will say Dev A, function 2 and
Dev B, function 3 etc. These become [EMAIL PROTECTED],2 and pci@ 1,3.
device/hypertransport.c:
Remove many #if statements and rely on the dts.
The idea here is that we change HT devices to PCI at enumeration.
That makes it so that they can be scanned on the normal PCI bus.
The code is set up so that it can also scan without being given ht
UnitIDs [EMAIL PROTECTED], and then it assigns them in the order it finds
them.
device/pci_device.c:
Add an error if there's a broken BAR.
Remove an overly verbose statement Not setting VID...
Add the path to a debug statement about leftover devices.
device/device_util.c:
Add HT support in dev_path().
device/pci_ops.c
Make the debug statement more clear when there's a loop.
northbridge/amd/k8/pci.c:
Remove offset_unitid
util/dtc/flattree.c:
Add support for [EMAIL PROTECTED],unitid.
Remove broken link code.
This code generated a new link when there was a sibling of a bridge
that was also a bridge. This breaks Serengeti because it has two
siblings that are bridges, but they are not on separate links.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Here's the resulting device tree:
Notice that the only dynamic (discovered) devices are the plug-in cards.
Show all devs in tree form...After phase 3.
root(Root Device): enabled 1 have_resources 0
cpus(CPU: 00): enabled 1 have_resources 0
apic_0(APIC: 00): enabled 1 have_resources 0
domain_0(PCI_DOMAIN: 0000): enabled 1 have_resources 0
domain_0_pci_18_0(PCI: 00:18.0): enabled 1 have_resources 0
domain_0_pci_18_0_ht_0_6(PCI: 00:06.0): enabled 1 have_resources 0
domain_0_pci_18_0_ht_0_6_pci_0_0(PCI: 01:00.0): enabled 1 have_resources
0
domain_0_pci_18_0_ht_0_6_pci_0_1(PCI: 01:00.1): enabled 1 have_resources
0
domain_0_pci_18_0_ht_0_6_pci_0_2(PCI: 01:00.2): enabled 0 have_resources
0
domain_0_pci_18_0_ht_0_6_pci_1_0(PCI: 01:01.0): enabled 0 have_resources
0
dynamic PCI: 01:04.0(PCI: 01:04.0): enabled 1 have_resources 0
dynamic PCI: 01:05.0(PCI: 01:05.0): enabled 1 have_resources 0
domain_0_pci_18_0_pci_6_1_0(PCI: 00:07.0): enabled 1 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e(IOPORT: 2e): enabled 1
have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_0(PNP: 002e.0): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_1(PNP: 002e.1): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_2(PNP: 002e.2): enabled
1 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_3(PNP: 002e.3): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_5(PNP: 002e.5): enabled
1 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_6(PNP: 002e.6): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_7(PNP: 002e.7): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_8(PNP: 002e.8): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_9(PNP: 002e.9): enabled
0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_10(PNP: 002e.a):
enabled 0 have_resources 0
domain_0_pci_18_0_pci_6_1_0_ioport_2e_pnp_child_11(PNP: 002e.b):
enabled 1 have_resources 0
domain_0_pci_18_0_pci_6_1_1(PCI: 00:07.1): enabled 1 have_resources 0
domain_0_pci_18_0_pci_6_1_2(PCI: 00:07.2): enabled 1 have_resources 0
domain_0_pci_18_0_pci_6_1_3(PCI: 00:07.3): enabled 1 have_resources 0
domain_0_pci_18_0_pci_6_1_5(PCI: 00:07.5): enabled 0 have_resources 0
domain_0_pci_18_0_pci_6_1_6(PCI: 00:07.6): enabled 0 have_resources 0
domain_0_pci_18_0_pci_6_1_7(PCI: 00:07.7): enabled 1 have_resources 0
domain_0_pci_18_0_ht_0_a(PCI: 00:0a.0): enabled 1 have_resources 0
domain_0_pci_18_0_pci_a_0_1(PCI: 00:0a.1): enabled 1 have_resources 0
domain_0_pci_18_0_pci_a_1_0(PCI: 00:0b.0): enabled 1 have_resources 0
domain_0_pci_18_0_pci_a_1_1(PCI: 00:0b.1): enabled 1 have_resources 0
domain_0_pci_18_1(PCI: 00:18.1): enabled 1 have_resources 0
domain_0_pci_18_2(PCI: 00:18.2): enabled 1 have_resources 0
domain_0_pci_18_3(PCI: 00:18.3): enabled 1 have_resources 0
I'm hoping that this gets us to the point where we can work on getting video
working.
Here are some of the next steps:
- Get video working.
- Remove #ifs from k8 chain code.
- Add the rest of the devices to the dts (other processors and AGP bridge.)
- Unify SIO code.
- Remove links structure? - K8 doesn't need them, does anyone?
Thanks,
Myles
Index: include/device/path.h
===================================================================
--- include/device/path.h (revision 1038)
+++ include/device/path.h (working copy)
@@ -24,6 +24,7 @@
DEVICE_PATH_PCI_DOMAIN,
DEVICE_PATH_PCI_BUS,
DEVICE_PATH_PCI,
+ DEVICE_PATH_HT,
DEVICE_PATH_PNP,
DEVICE_PATH_I2C,
DEVICE_PATH_APIC,
@@ -41,6 +42,11 @@
unsigned bus;
};
+struct ht_path {
+ unsigned chain;
+ unsigned unitid;
+};
+
struct pci_path {
unsigned devfn;
};
@@ -80,6 +86,7 @@
enum device_path_type type;
union {
struct pci_path pci;
+ struct ht_path ht;
struct pnp_path pnp;
struct i2c_path i2c;
struct apic_path apic;
Index: include/device/hypertransport.h
===================================================================
--- include/device/hypertransport.h (revision 1038)
+++ include/device/hypertransport.h (working copy)
@@ -22,7 +22,7 @@
#include <device/hypertransport_def.h>
unsigned int hypertransport_scan_chain(struct bus *bus,
- unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid);
+ unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base);
unsigned int ht_scan_bridge(struct device *dev, unsigned int max);
extern const struct device_operations default_ht_ops_bus;
Index: mainboard/amd/serengeti/dts
===================================================================
--- mainboard/amd/serengeti/dts (revision 1038)
+++ mainboard/amd/serengeti/dts (working copy)
@@ -27,9 +27,21 @@
};
[EMAIL PROTECTED] {
/config/("northbridge/amd/k8/domain");
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("northbridge/amd/k8/pci");
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],a {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
+ [EMAIL PROTECTED],1{
+ /config/("southbridge/amd/amd8132/apic.dts");
+ };
+ [EMAIL PROTECTED],0 {
+ /config/("southbridge/amd/amd8132/pcix.dts");
+ };
+ [EMAIL PROTECTED],1{
+ /config/("southbridge/amd/amd8132/apic.dts");
+ };
+ [EMAIL PROTECTED],6 {
/config/("southbridge/amd/amd8111/pci.dts");
[EMAIL PROTECTED],0{
/config/("southbridge/amd/amd8111/usb.dts");
@@ -39,51 +51,52 @@
};
[EMAIL PROTECTED],2{
/config/("southbridge/amd/amd8111/usb2.dts");
- disable;
+ disabled;
};
[EMAIL PROTECTED],0{
/config/("southbridge/amd/amd8111/nic.dts");
- disable;
+ disabled;
};
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/amd8111/lpc.dts");
+ [EMAIL PROTECTED] {
+ /config/("superio/winbond/w83627hf/dts");
+ kbenable = "1";
+ com1enable = "1";
+ hwmenable = "1";
+ };
};
- [EMAIL PROTECTED],1 {
+ [EMAIL PROTECTED],1 {
/config/("southbridge/amd/amd8111/ide.dts");
ide0_enable = "1";
ide1_enable = "1";
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/amd8111/smbus.dts");
};
- [EMAIL PROTECTED],3 {
+ [EMAIL PROTECTED],3 {
/config/("southbridge/amd/amd8111/acpi.dts");
};
- [EMAIL PROTECTED],5 {
+ [EMAIL PROTECTED],5 {
/config/("southbridge/amd/amd8111/ac97audio.dts");
+ disabled;
};
- [EMAIL PROTECTED],6 {
+ [EMAIL PROTECTED],6 {
/config/("southbridge/amd/amd8111/ac97modem.dts");
+ disabled;
};
- [EMAIL PROTECTED],0 {
- /config/("southbridge/amd/amd8132/pcix.dts");
+ [EMAIL PROTECTED],7 {
};
};
- [EMAIL PROTECTED],0 {
- /config/("northbridge/amd/k8/pci");
- };
- [EMAIL PROTECTED],0 {
- /config/("northbridge/amd/k8/pci");
- };
[EMAIL PROTECTED],1 {};
[EMAIL PROTECTED],2 {};
[EMAIL PROTECTED],3 {};
+ [EMAIL PROTECTED],0 {
+ /config/("northbridge/amd/k8/pci");
+ };
+ [EMAIL PROTECTED],1 {};
+ [EMAIL PROTECTED],2 {};
+ [EMAIL PROTECTED],3 {};
};
- [EMAIL PROTECTED] {
- /config/("superio/winbond/w83627hf/dts");
- kbenable = "1";
- com1enable = "1";
- hwmenable = "1";
- };
};
Index: device/hypertransport.c
===================================================================
--- device/hypertransport.c (revision 1038)
+++ device/hypertransport.c (working copy)
@@ -39,11 +39,11 @@
#include <device/hypertransport.h>
#include <mc146818rtc.h>
#include <lib.h>
-#include <lapic.h>
+#include <lapic.h>
#define OPT_HT_LINK 0
-static struct device *ht_scan_get_devs(struct device **old_devices)
+static struct device *ht_get_devs(struct device **old_devices)
{
struct device *first, *last;
first = *old_devices;
@@ -53,8 +53,7 @@
* for the next hypertransport device.
*/
while (last && last->sibling &&
- (last->sibling->path.type == DEVICE_PATH_PCI) &&
- (last->sibling->path.pci.devfn > last->path.pci.devfn)) {
+ (last->sibling->path.type != DEVICE_PATH_HT)) {
last = last->sibling;
}
if (first) {
@@ -68,7 +67,7 @@
for (child = first->bus->children; child && child->sibling;) {
child = child->sibling;
}
- /* Place the chain on the list of children of their parent. */
+ /* Place the chain on the head of the list of children. */
if (child) {
child->sibling = first;
} else {
@@ -287,8 +286,7 @@
return pos;
}
-static void ht_collapse_early_enumeration(struct bus *bus,
- unsigned int offset_unitid)
+static void ht_collapse_early_enumeration(struct bus *bus)
{
unsigned int devfn, ctrl;
struct ht_link prev;
@@ -326,31 +324,6 @@
}
} while ((ctrl & (1 << 5)) == 0);
- /* Actually, only for one HT device HT chain, and unitid is 0. */
-#if HT_CHAIN_UNITID_BASE == 0
- if (offset_unitid) {
- return;
- }
-#endif
-
- /* Check if is already collapsed. */
- if ((!offset_unitid)
- || (offset_unitid
- &&
- (!((HT_CHAIN_END_UNITID_BASE == 0)
- && (HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE))))) {
- struct device dummy;
- u32 id;
- dummy.bus = bus;
- dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.pci.devfn = PCI_DEVFN(0, 0);
- id = pci_read_config32(&dummy, PCI_VENDOR_ID);
- if (!((id == 0xffffffff) || (id == 0x00000000) ||
- (id == 0x0000ffff) || (id == 0xffff0000))) {
- return;
- }
- }
-
/* Spin through the devices and collapse any early
* hypertransport enumeration.
*/
@@ -387,31 +360,20 @@
unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn,
unsigned int max,
- unsigned int *ht_unitid_base,
- unsigned int offset_unitid)
+ unsigned int *ht_unitid_base)
{
- /* Even HT_CHAIN_UNITID_BASE == 0, we still can go through this
- * function, because of end_of_chain check, also we need it to
- * optimize link.
+ /* We need this function for the end_of_chain check, also we need it to
+ * optimize the link.
*/
- unsigned int next_unitid, last_unitid;
+ unsigned int next_unitid, new_unitid;
+ unsigned int saved_unitid, min_unitid;
struct device *old_devices, *dev, *func;
- unsigned int min_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE : 1;
struct ht_link prev;
struct device *last_func = 0;
int ht_dev_num = 0;
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
- /* Let's record the device of last HT device, so we can set the
- * unitid to HT_CHAIN_END_UNITID_BASE.
- */
- unsigned int real_last_unitid = 0;
- u8 real_last_pos = 0;
- struct device *real_last_dev = NULL;
-#endif
-
/* Restore the hypertransport chain to its unitialized state. */
- ht_collapse_early_enumeration(bus, offset_unitid);
+ ht_collapse_early_enumeration(bus);
/* See which static device nodes I have. */
old_devices = bus->children;
@@ -426,15 +388,13 @@
prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
/* If present assign unitid to a hypertransport chain. */
- last_unitid = min_unitid - 1;
- next_unitid = min_unitid;
+ next_unitid = PCI_SLOT(min_devfn);
+ min_unitid = 0xff;
do {
u8 pos;
u16 flags;
unsigned int count, static_count, ctrl;
- last_unitid = next_unitid;
-
/* Wait until the link initialization is complete. */
do {
ctrl = pci_read_config16(prev.dev,
@@ -463,8 +423,32 @@
} while ((ctrl & (1 << 5)) == 0);
/* Get and setup the device_structure. */
- dev = ht_scan_get_devs(&old_devices);
+ dev = ht_get_devs(&old_devices);
+ printk(BIOS_DEBUG, "%s: ht_get_devs returns %s, probing\n",
+ __func__, dev? dev_path(dev):"NULL");
+
+ /* Save the UnitID from the tree, or zero if not there.
+ * Convert device to PCI. There's no use for HT after this.
+ */
+ if (dev)
+ {
+ if ( dev->path.type != DEVICE_PATH_HT )
+ printk(BIOS_ERR, "%s: %s(%s) in HT chain.\n",
+ __func__, dev->dtsname, dev_path(dev));
+
+ if ( dev->path.ht.unitid != 0xff )
+ saved_unitid = dev->path.ht.unitid;
+ else
+ saved_unitid = 0xff;
+
+ /* pci_probe_dev will fail if devfn != 0.*/
+ dev->path.type = DEVICE_PATH_PCI;
+ dev->path.pci.devfn = PCI_DEVFN(0,0);
+ }
+ else
+ saved_unitid = 0xff;
+
/* See if a device is present and setup the device structure. */
dev = pci_probe_dev(dev, bus, 0);
if (!dev || !dev->enabled) {
@@ -488,23 +472,43 @@
* device chain.
*/
if (flags & 0x1f) {
+ printk(BIOS_DEBUG, "End of chain: this device didn't collapse.\n");
+ printk(BIOS_DEBUG, "flags = %04x UnitID = %02x UnitIDs = %02x\n",
+ flags, flags & 0x1f, (flags >> 4) & 0x1f);
break;
}
flags &= ~0x1f; /* Mask out base Unit ID. */
- flags |= next_unitid & 0x1f;
+ if (saved_unitid != 0xff)
+ new_unitid = saved_unitid;
+ else
+ new_unitid = next_unitid;
+
+ if (min_unitid > new_unitid)
+ min_unitid = new_unitid;
+
+ flags |= new_unitid & 0x1f;
pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
- /* Update the unitid in the device structure. */
+ /* Update the UnitID in the device structure. */
+ printk(BIOS_SPEW, "%s new_unitid %02x devfn %02x\n",
+ dev->dtsname, new_unitid, dev->path.pci.devfn);
+
static_count = 1;
for (func = dev; func; func = func->sibling) {
- func->path.pci.devfn += (next_unitid << 3);
- static_count = (func->path.pci.devfn >> 3)
- - (dev->path.pci.devfn >> 3) + 1;
+ func->path.pci.devfn += PCI_DEVFN(new_unitid,0);
+ static_count = PCI_SLOT(func->path.pci.devfn)
+ - PCI_SLOT(dev->path.pci.devfn) + 1;
last_func = func;
}
+ printk(BIOS_SPEW, "%s new_unitid %02x devfn %02x\n",
+ dev->dtsname, new_unitid, dev->path.pci.devfn);
- /* Compute the number of unitids consumed. */
+ if (pci_read_config16(dev, pos + PCI_CAP_FLAGS) != flags)
+ printk(BIOS_ERR, "%s couldn't update UnitID! flags=%02x wrote %02x\n",
+ dev->dtsname, pci_read_config16(dev, pos + PCI_CAP_FLAGS),flags);
+
+ /* Compute the number of UnitIDs consumed. */
count = (flags >> 5) & 0x1f; /* Get unit count. */
printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
dev_path(dev), count, static_count);
@@ -512,29 +516,25 @@
count = static_count;
}
- /* Update the unitid of the next device. */
- ht_unitid_base[ht_dev_num] = next_unitid;
+ /* Update the unitid of the device. */
+ ht_unitid_base[ht_dev_num] = new_unitid;
ht_dev_num++;
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
- if (offset_unitid) {
- real_last_unitid = next_unitid;
- real_last_pos = pos;
- real_last_dev = dev;
- }
-#endif
- next_unitid += count;
+ /* Only increment if we used the top UnitID's. */
+ if (next_unitid <= new_unitid)
+ next_unitid = new_unitid + count;
+
/* Setup the hypertransport link. */
bus->reset_needed |= ht_setup_link(&prev, dev, pos);
- printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
+ printk(BIOS_DEBUG, "%s [%04x/%04x] %s new_unitid: %04x\n",
dev_path(dev),
dev->id.pci.vendor, dev->id.pci.device,
(dev->enabled ? "enabled" : "disabled"),
- next_unitid);
+ new_unitid);
- } while ((last_unitid != next_unitid)
- && (next_unitid <= (max_devfn >> 3)));
+ } while ((next_unitid <= PCI_SLOT(max_devfn)));
+
end_of_chain:
#if OPT_HT_LINK == 1
if (bus->reset_needed) {
@@ -544,38 +544,14 @@
}
#endif
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
- if (offset_unitid && (ht_dev_num > 0)) {
- u16 flags;
- struct device *last_func = 0;
- flags = pci_read_config16(real_last_dev,
- real_last_pos + PCI_CAP_FLAGS);
- flags &= ~0x1f;
- flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
- pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS,
- flags);
-
- for (func = real_last_dev; func; func = func->sibling) {
- func->path.pci.devfn -=
- ((real_last_unitid -
- HT_CHAIN_END_UNITID_BASE) << 3);
- last_func = func;
- }
-
- /* Update last one. */
- ht_unitid_base[ht_dev_num - 1] = HT_CHAIN_END_UNITID_BASE;
-
- next_unitid = real_last_unitid;
- }
-#endif
-
if (next_unitid > 0x1f) {
+ printk(BIOS_ERR, "More devices %02x than allowed 0x1f!\n",
+ next_unitid);
next_unitid = 0x1f;
}
/* Die if any leftover static devices are found.
- * There's probably a problem in the Config.lb.
- * TODO: No more Config.lb in coreboot-v3.
+ * There's probably a problem in the dts.
*/
if (old_devices) {
struct device *left;
@@ -584,17 +560,26 @@
printk(BIOS_INFO, "%s\n", dev_path(left));
}
printk(BIOS_INFO, "HT: End of leftover list.\n");
- /* Put back the left over static device, and let
- * pci_scan_bus() disable it.
+ /* Put the left over static devices at the end, and let
+ * pci_scan_bus() disable them.
*/
- if (last_func && !last_func->sibling)
+ if (last_func && !last_func->sibling){
+
last_func->sibling = old_devices;
+ printk(BIOS_INFO, "HT: putting leftovers as siblings to %s\n",
+ last_func->dtsname);
+ }
+
+ printk(BIOS_INFO, "HT: End of leftover list.\n");
}
/* Now that nothing is overlapping it is safe to scan the
* children.
*/
- max = pci_scan_bus(bus, 0x00, (next_unitid << 3) | 7, max);
+ printk(BIOS_INFO, "Ready to scan: next_unitid = %02x max = %02x.\n",
+ next_unitid,max);
+ /* Should we not scan the bus if no HT devices were found? Probably */
+ max = pci_scan_bus(bus, PCI_DEVFN(min_unitid,0), PCI_DEVFN(next_unitid, 0x7), max);
return max;
}
@@ -620,9 +605,8 @@
unsigned int max)
{
unsigned int ht_unitid_base[4];
- unsigned int offset_unitid = 1;
return hypertransport_scan_chain(bus, min_devfn, max_devfn, max,
- ht_unitid_base, offset_unitid);
+ ht_unitid_base);
}
unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
Index: device/pci_device.c
===================================================================
--- device/pci_device.c (revision 1038)
+++ device/pci_device.c (working copy)
@@ -248,6 +248,8 @@
resource->limit = 0xffffffffffffffffULL;
} else {
/* Invalid value. */
+ printk(BIOS_ERR,"Broken BAR %s:%02lx=%lx\n",
+ dev->dtsname,index,attr);
resource->flags = 0;
}
}
@@ -355,7 +357,7 @@
{
/* Initialize the constraints on the current bus. */
struct resource *resource;
- resource = 0;
+ resource = NULL;
if (moving) {
unsigned long gran;
resource_t step;
@@ -660,10 +662,7 @@
dev_path(dev), vendor, device);
ops->set_subsystem(dev, vendor, device);
- } else {
- printk(BIOS_DEBUG, "%s: Not setting subsystem VID/DID\n",
- dev_path(dev));
- }
+ }
}
@@ -1187,7 +1186,8 @@
struct device *left;
printk(BIOS_INFO, "PCI: Left over static devices:\n");
for (left = old_devices; left; left = left->sibling) {
- printk(BIOS_INFO, "%s\n", left->dtsname);
+ printk(BIOS_INFO, "%s(%s)\n", left->dtsname,
+ dev_path(left));
}
printk(BIOS_INFO, "PCI: End of leftover list.\n");
}
Index: device/device_util.c
===================================================================
--- device/device_util.c (revision 1038)
+++ device/device_util.c (working copy)
@@ -208,6 +208,11 @@
PCI_FUNC(dev->path.pci.devfn));
#endif
break;
+ case DEVICE_PATH_HT:
+ sprintf(buffer, "HT(%02x): %02x",
+ dev->path.ht.chain,
+ dev->path.ht.unitid);
+ break;
case DEVICE_PATH_PNP:
sprintf(buffer, "PNP: %04x.%01x",
dev->path.pnp.port, dev->path.pnp.device);
Index: device/pci_ops.c
===================================================================
--- device/pci_ops.c (revision 1038)
+++ device/pci_ops.c (working copy)
@@ -36,7 +36,7 @@
struct bus *pbus = dev->bus;
while (pbus && pbus->dev && !ops_pci_bus(pbus)) {
if (pbus->dev == dev) {
- printk(BIOS_EMERG, "Loop: dev->dtsname dev->bus->dev\n");
+ printk(BIOS_EMERG, "Loop: %s->bus->dev\n", dev->dtsname);
printk(BIOS_EMERG, "To fix this, set ops_pci_bus in dts\n");
die("loop due to insufficient dts");
}
Index: northbridge/amd/k8/pci.c
===================================================================
--- northbridge/amd/k8/pci.c (revision 1038)
+++ northbridge/amd/k8/pci.c (working copy)
@@ -53,7 +53,7 @@
void f1_write_config32(unsigned int reg, u32 value);
unsigned int amdk8_nodeid(struct device * dev);
-static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
+static unsigned int amdk8_scan_chain(struct device * dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max)
{
u32 link_type;
@@ -172,7 +172,7 @@
else
max_devfn = (0x1f<<3) | 7;
- max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
+ max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base);
/* We know the number of busses behind this bridge. Set the
* subordinate bus number to it's real value
@@ -208,7 +208,6 @@
unsigned nodeid;
unsigned link;
unsigned sblink = 0;
- unsigned offset_unitid = 0;
nodeid = amdk8_nodeid(dev);
printk(BIOS_DEBUG, "amdk8_scan_chains\n");
@@ -216,12 +215,9 @@
if(nodeid==0) {
sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
#if SB_HT_CHAIN_ON_BUS0 > 0
- #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
- offset_unitid = 1;
- #endif
// do southbridge ht chain first, in case s2885 put southbridge chain (8131/8111) on link2,
// but put 8151 on link0
- max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid );
+ max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max);
#endif
}
@@ -229,15 +225,13 @@
#if SB_HT_CHAIN_ON_BUS0 > 0
if( (nodeid == 0) && (sblink == link) ) continue; //already done
#endif
- offset_unitid = 0;
#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20))
#if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
if((nodeid == 0) && (sblink == link))
#endif
- offset_unitid = 1;
#endif
- max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
+ max = amdk8_scan_chain(dev, nodeid, link, sblink, max);
}
return max;
Index: util/dtc/flattree.c
===================================================================
--- util/dtc/flattree.c (revision 1038)
+++ util/dtc/flattree.c (working copy)
@@ -610,6 +610,26 @@
fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n",
dev, fn);
}
+ if (!strncmp(tree->name, "ht", 2)){
+ /* it's in two parts */
+ char *ht_path = strdup(path);
+ char *chain = ht_path;
+ char *unitid;
+
+ unitid = index(ht_path, ',');
+ /* If there is no UnitID we set it to -1. */
+ if (unitid)
+ *unitid++ = 0;
+ else
+ unitid = "ff";
+
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_HT,{.ht={ .chain = 0x%s, .unitid = 0x%s}}},\n",
+ chain, unitid);
+ }
+ if (!strncmp(tree->name, "pnp", 3)){
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_PNP,{.pnp={ .device=0x%s}}},\n",
+ path);
+ }
if (!strncmp(tree->name, "ioport", 6)){
fprintf(f, "\t.path = {.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x%s}}},\n",
path);
@@ -701,7 +721,7 @@
* There is a good chance we could expand the for loop to contain this first bit of code.
* OTOH, the compiler can do it for us, and the initial conditions are clearer this way.
*/
- if ((! tree->linked) && is_bridge(tree)){
+ if (is_bridge(tree)){
struct node *siblings;
fprintf(f,"\t.link = {\n");
fprintf(f,"\t\t[%d] = {\n", linkcount);
@@ -712,24 +732,6 @@
fprintf(f,"\t\t},\n");
/* now we need to handle our siblings. */
linkcount++;
- for_all_siblings(tree, siblings) {
- if (is_bridge(siblings) && (!siblings->linked)){
- fprintf(f,"\t\t[%d] = {\n", linkcount);
- fprintf(f,"\t\t\t.dev = &dev_%s,\n", siblings->label);
- fprintf(f,"\t\t\t.link = %d,\n", linkcount);
- if (siblings->children) {
- fprintf(f,"\t\t\t.children = &dev_%s\n", siblings->children->label);
- siblings->children->linked = 1;
- siblings->children->linknode = tree;
- siblings->children->whichlink = linkcount;
- }
- fprintf(f,"\t\t},\n");
- siblings->linked = 1;
- siblings->whichlink = linkcount;
- siblings->linknode = tree;
- linkcount++;
- }
- }
fprintf(f,"\t},\n");
}
fprintf(f,"\t.links = %d,\n", linkcount);
--
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