On 11/19/08, Carl-Daniel Hailfinger <[EMAIL PROTECTED]> wrote: > On ICH SPI, page_size is the maximum number of bytes you can write and > read in one operation. ICH SPI hardcodes eraseblock size to 4k. ITE SPI > is different.
Point me to the exact place of documentation if convenient? I have been reading(quick browsing) the ICH7 spec., but have not found this limitation yet(or just forgotten immediately). I have been reading various docs these days. > I sent a patch to use explicit erase block sizes, but that patch does > not have any Ack yet. About when? Maybe I can help search for it. BTW, I have not finished reading ichspi.c, but ask previously, are we able to write a part of the chip in ichspi.c(to support ROM layout)? yu ning -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
