Author: myles
Date: 2008-11-24 15:06:10 +0100 (Mon, 24 Nov 2008)
New Revision: 1048
Modified:
coreboot-v3/device/agp_device.c
coreboot-v3/device/cardbus_device.c
coreboot-v3/device/hypertransport.c
coreboot-v3/device/pci_device.c
coreboot-v3/device/pcie_device.c
coreboot-v3/device/pcix_device.c
coreboot-v3/include/device/pci.h
coreboot-v3/mainboard/emulation/qemu-x86/vga.c
coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c
coreboot-v3/northbridge/intel/i945/northbridge.c
coreboot-v3/northbridge/via/cn700/agp.c
coreboot-v3/northbridge/via/cn700/pci.c
coreboot-v3/northbridge/via/cn700/vga.c
coreboot-v3/southbridge/amd/amd8111/ac97.c
coreboot-v3/southbridge/amd/amd8111/acpi.c
coreboot-v3/southbridge/amd/amd8111/ide.c
coreboot-v3/southbridge/amd/amd8111/lpc.c
coreboot-v3/southbridge/amd/amd8111/nic.c
coreboot-v3/southbridge/amd/amd8111/pci.c
coreboot-v3/southbridge/amd/amd8111/smbus.c
coreboot-v3/southbridge/amd/amd8111/usb.c
coreboot-v3/southbridge/amd/amd8111/usb2.c
coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c
coreboot-v3/southbridge/amd/cs5536/cs5536.c
coreboot-v3/southbridge/amd/rs690/gfx.c
coreboot-v3/southbridge/amd/rs690/ht.c
coreboot-v3/southbridge/amd/rs690/pcie.c
coreboot-v3/southbridge/amd/sb600/ac97.c
coreboot-v3/southbridge/amd/sb600/hda.c
coreboot-v3/southbridge/amd/sb600/ide.c
coreboot-v3/southbridge/amd/sb600/lpc.c
coreboot-v3/southbridge/amd/sb600/pci.c
coreboot-v3/southbridge/amd/sb600/sata.c
coreboot-v3/southbridge/amd/sb600/sm.c
coreboot-v3/southbridge/amd/sb600/usb.c
coreboot-v3/southbridge/intel/i82371eb/i82371eb.c
coreboot-v3/southbridge/intel/i82801gx/ac97.c
coreboot-v3/southbridge/intel/i82801gx/ide.c
coreboot-v3/southbridge/intel/i82801gx/lpc.c
coreboot-v3/southbridge/intel/i82801gx/nic.c
coreboot-v3/southbridge/intel/i82801gx/pci.c
coreboot-v3/southbridge/intel/i82801gx/pcie.c
coreboot-v3/southbridge/intel/i82801gx/sata.c
coreboot-v3/southbridge/intel/i82801gx/smbus.c
coreboot-v3/southbridge/intel/i82801gx/usb.c
coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c
coreboot-v3/southbridge/nvidia/mcp55/ide.c
coreboot-v3/southbridge/nvidia/mcp55/lpc.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
coreboot-v3/southbridge/nvidia/mcp55/pci.c
coreboot-v3/southbridge/nvidia/mcp55/pcie.c
coreboot-v3/southbridge/nvidia/mcp55/sata.c
coreboot-v3/southbridge/nvidia/mcp55/smbus.c
coreboot-v3/southbridge/nvidia/mcp55/usb.c
coreboot-v3/southbridge/nvidia/mcp55/usb2.c
coreboot-v3/southbridge/via/vt8237/ide.c
coreboot-v3/southbridge/via/vt8237/lpc.c
coreboot-v3/southbridge/via/vt8237/sata.c
Log:
This patch changes all occurrences of pci_dev_set_resources ->
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
Modified: coreboot-v3/device/agp_device.c
===================================================================
--- coreboot-v3/device/agp_device.c 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/device/agp_device.c 2008-11-24 14:06:10 UTC (rev 1048)
@@ -61,7 +61,7 @@
const struct device_operations default_agp_ops_bus = {
.read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
+ .set_resources = pci_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = 0,
.scan_bus = agp_scan_bridge,
Modified: coreboot-v3/device/cardbus_device.c
===================================================================
--- coreboot-v3/device/cardbus_device.c 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/device/cardbus_device.c 2008-11-24 14:06:10 UTC (rev 1048)
@@ -244,7 +244,7 @@
const struct device_operations default_cardbus_ops_bus = {
.phase3_scan = cardbus_scan_bridge,
.phase4_read_resources = cardbus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = cardbus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,
Modified: coreboot-v3/device/hypertransport.c
===================================================================
--- coreboot-v3/device/hypertransport.c 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/device/hypertransport.c 2008-11-24 14:06:10 UTC (rev 1048)
@@ -638,7 +638,7 @@
const struct device_operations default_ht_ops_bus = {
.phase3_scan = ht_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,
Modified: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3/device/pci_device.c 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/device/pci_device.c 2008-11-24 14:06:10 UTC (rev 1048)
@@ -567,7 +567,7 @@
return;
}
-void pci_dev_set_resources(struct device *dev)
+void pci_set_resources(struct device *dev)
{
struct resource *resource, *last;
unsigned int link;
@@ -742,7 +742,7 @@
const struct device_operations default_pci_ops_dev = {
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pci_dev_init,
.phase3_scan = 0,
@@ -757,7 +757,7 @@
const struct device_operations default_pci_ops_bus = {
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,
Modified: coreboot-v3/device/pcie_device.c
===================================================================
--- coreboot-v3/device/pcie_device.c 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/device/pcie_device.c 2008-11-24 14:06:10 UTC (rev 1048)
@@ -64,7 +64,7 @@
const struct device_operations default_pcie_ops_bus = {
.phase3_scan = pcie_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.reset_bus = pci_bus_reset,
Modified: coreboot-v3/device/pcix_device.c
===================================================================
--- coreboot-v3/device/pcix_device.c 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/device/pcix_device.c 2008-11-24 14:06:10 UTC (rev 1048)
@@ -142,7 +142,7 @@
struct device_operations default_pcix_ops_bus = {
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = 0,
.phase3_scan = pcix_scan_bridge,
Modified: coreboot-v3/include/device/pci.h
===================================================================
--- coreboot-v3/include/device/pci.h 2008-11-20 12:20:35 UTC (rev 1047)
+++ coreboot-v3/include/device/pci.h 2008-11-24 14:06:10 UTC (rev 1048)
@@ -78,7 +78,7 @@
void pci_dev_read_resources(struct device * dev);
void pci_bus_read_resources(struct device * dev);
-void pci_dev_set_resources(struct device * dev);
+void pci_set_resources(struct device * dev);
void pci_dev_enable_resources(struct device * dev);
void pci_bus_enable_resources(struct device * dev);
void pci_bus_reset(struct bus *bus);
Modified: coreboot-v3/mainboard/emulation/qemu-x86/vga.c
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -53,7 +53,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = setup_onboard,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/mainboard/kontron/986lcd-m/rtl8168.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -43,7 +43,7 @@
.device = 0x8168}}},
.constructor = default_device_constructor,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = nic_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -197,6 +197,7 @@
pci_dev_read_resources(dev);
+#warning After we fix the allocator we need to fix this!
/* So, this is one of the big mysteries in the coreboot resource
* allocator. This resource should make sure that the address space
* of the PCIe memory mapped config space bar. But it does not.
@@ -226,7 +227,7 @@
}
/* And call the normal set_resources */
- pci_dev_set_resources(dev);
+ pci_set_resources(dev);
}
static void intel_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
Modified: coreboot-v3/northbridge/via/cn700/agp.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/agp.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/northbridge/via/cn700/agp.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -108,7 +108,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_dev_set_resources,
+ //.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = agp_init,
};
Modified: coreboot-v3/northbridge/via/cn700/pci.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/pci.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/northbridge/via/cn700/pci.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -55,7 +55,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_dev_set_resources,
+ //.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pci_bridge_init,
};
Modified: coreboot-v3/northbridge/via/cn700/vga.c
===================================================================
--- coreboot-v3/northbridge/via/cn700/vga.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/northbridge/via/cn700/vga.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -73,7 +73,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vga_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = vga_init,
};
Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -46,7 +46,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
@@ -60,7 +60,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -233,7 +233,7 @@
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = acpi_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = acpi_enable_resources,
.phase6_init = acpi_init,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/amd8111/ide.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -80,7 +80,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &lops_pci
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -215,7 +215,7 @@
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = amd8111_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = amd8111_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/amd8111/nic.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -101,7 +101,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = nic_init,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/amd8111/pci.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/pci.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/pci.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -77,7 +77,7 @@
.phase3_scan = pci_scan_bridge,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
};
Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -55,7 +55,7 @@
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/amd8111/usb.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -52,7 +52,7 @@
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci
Modified: coreboot-v3/southbridge/amd/amd8111/usb2.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/amd8111/usb2.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -51,7 +51,7 @@
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = amd8111_usb2_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
};
Modified: coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-11-20
12:20:35 UTC (rev 1047)
+++ coreboot-v3/southbridge/amd/amd8132/amd8132_bridge.c 2008-11-24
14:06:10 UTC (rev 1048)
@@ -340,7 +340,7 @@
report_resource_stored(dev, res, "including NPUML");
}
- pci_dev_set_resources(dev);
+ pci_set_resources(dev);
}
struct device_operations amd8132_pcix = {
@@ -420,7 +420,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = ioapic_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = amd8132_ioapic_init,
.ops_pci = &pci_ops_pci_dev,
Modified: coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/amd/amd8151/amd8151_agp3.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -47,7 +47,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = agp3bridge_init,
};
@@ -82,7 +82,7 @@
.constructor = default_device_constructor,
.phase4_enable_disable = agp3dev_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -696,7 +696,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = cs5536_pci_dev_enable_resources,
.phase6_init = southbridge_init,
};
@@ -709,7 +709,7 @@
#warning FIXME: what has to go in phase3_scan?
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/amd/rs690/gfx.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/gfx.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/rs690/gfx.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -109,8 +109,9 @@
static void rs690_gfx_set_resources(struct device *dev)
{
+#warning This does nothing. Implement it or remove it.
printk(BIOS_INFO, "rs690_gfx_set_resources.\n");
- pci_dev_set_resources(dev);
+ pci_set_resources(dev);
}
/*
Modified: coreboot-v3/southbridge/amd/rs690/ht.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/ht.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/rs690/ht.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -88,7 +88,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = rs690_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/rs690/pcie.c
===================================================================
--- coreboot-v3/southbridge/amd/rs690/pcie.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/rs690/pcie.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -402,7 +402,7 @@
.phase3_scan = pci_scan_bridge,
.phase3_chip_setup_dev = rs690_enable,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -416,7 +416,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -429,7 +429,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -442,7 +442,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -455,7 +455,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -468,7 +468,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -481,7 +481,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
@@ -494,7 +494,7 @@
.constructor = default_device_constructor,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/sb600/ac97.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/ac97.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/ac97.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -40,7 +40,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
@@ -54,7 +54,7 @@
.phase3_scan = 0,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = NULL,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/amd/sb600/hda.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/hda.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/hda.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -281,7 +281,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = hda_init,
.ops_pci = &lops_pci
Modified: coreboot-v3/southbridge/amd/sb600/ide.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/ide.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/ide.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -72,7 +72,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &lops_pci
Modified: coreboot-v3/southbridge/amd/sb600/lpc.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/lpc.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/lpc.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -215,7 +215,7 @@
.phase3_scan = scan_static_bus,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = sb600_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = sb600_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &lops_pci
Modified: coreboot-v3/southbridge/amd/sb600/pci.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/pci.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/pci.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -132,7 +132,7 @@
.phase3_scan = pci_scan_bridge,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.reset_bus = pci_bus_reset,
Modified: coreboot-v3/southbridge/amd/sb600/sata.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sata.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/sata.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -194,7 +194,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = sb600_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &lops_pci
Modified: coreboot-v3/southbridge/amd/sb600/sm.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/sm.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/sm.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -376,11 +376,12 @@
compact_resources(dev);
}
+
static void sb600_sm_set_resources(struct device *dev)
{
struct resource *res;
- pci_dev_set_resources(dev);
+ pci_set_resources(dev);
res = find_resource(dev, 0x74);
pci_write_config32(dev, 0x74, res->base | 1 << 3);
Modified: coreboot-v3/southbridge/amd/sb600/usb.c
===================================================================
--- coreboot-v3/southbridge/amd/sb600/usb.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/amd/sb600/usb.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -143,7 +143,7 @@
old_debug = get_ehci_debug();
set_ehci_debug(0);
#endif
- pci_dev_set_resources(dev);
+ pci_set_resources(dev);
#ifdef CONFIG_USBDEBUG_DIRECT
res = find_resource(dev, 0x10);
Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -93,7 +93,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = i82371eb_isa_init,
.ops_pci = &pci_dev_ops_pci,
@@ -105,7 +105,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = i82371eb_ide_init,
.ops_pci = &pci_dev_ops_pci,
@@ -117,7 +117,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = i82371eb_acpi_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/ac97.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/ac97.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/ac97.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -49,7 +49,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ac97_audio_init,
.ops_pci = &pci_dev_ops_pci,
@@ -65,7 +65,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ac97_modem_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/ide.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/ide.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/ide.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -97,7 +97,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = ide_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/lpc.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -343,7 +343,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = i82801gx_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = i82801gx_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &pci_ops,
@@ -360,7 +360,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = i82801gx_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = i82801gx_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &pci_ops,
@@ -376,7 +376,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = i82801gx_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = i82801gx_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &pci_ops,
Modified: coreboot-v3/southbridge/intel/i82801gx/nic.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/nic.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/nic.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -44,7 +44,7 @@
.device = 0x27dc}}},
.constructor = default_device_constructor,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = nic_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/pci.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/pci.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/pci.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -132,7 +132,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = ich_pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@@ -148,7 +148,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = ich_pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/pcie.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/pcie.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/pcie.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -89,7 +89,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@@ -104,7 +104,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@@ -119,7 +119,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@@ -134,7 +134,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@@ -149,7 +149,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
@@ -164,7 +164,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_bus_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/sata.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/sata.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/sata.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -150,7 +150,7 @@
.reset_bus = pci_bus_reset,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &pci_dev_ops_pci,
@@ -198,4 +198,4 @@
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x27c6,
};
-#endif
\ No newline at end of file
+#endif
Modified: coreboot-v3/southbridge/intel/i82801gx/smbus.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/smbus.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/smbus.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -56,7 +56,7 @@
.phase3_chip_setup_dev = i82801gx_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci,
.ops_smbus_bus = &lops_smbus_bus,
Modified: coreboot-v3/southbridge/intel/i82801gx/usb.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/usb.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/usb.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -56,7 +56,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
@@ -70,7 +70,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
@@ -84,7 +84,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
@@ -98,7 +98,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -80,7 +80,7 @@
.constructor = default_device_constructor,
.phase3_chip_setup_dev = i82801gx_enable,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = usb_ehci_init,
.ops_pci = &lops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -77,7 +77,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -345,7 +345,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -358,7 +358,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -371,7 +371,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -384,7 +384,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -397,7 +397,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -410,7 +410,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -423,7 +423,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -436,7 +436,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_lpc_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = lpc_slave_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -267,7 +267,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = mcp55_enable,
.phase6_init = NULL,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -96,7 +96,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -54,7 +54,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -68,7 +68,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -82,7 +82,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -96,7 +96,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
@@ -110,7 +110,7 @@
.reset_bus = pci_bus_reset,
.phase3_scan = pci_scan_bridge,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -76,7 +76,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/smbus.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/smbus.c 2008-11-20 12:20:35 UTC
(rev 1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/smbus.c 2008-11-24 14:06:10 UTC
(rev 1048)
@@ -136,7 +136,7 @@
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_sm_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = mcp55_sm_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/usb.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/usb.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/usb.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -43,7 +43,7 @@
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
.ops_pci = &mcp55_pci_dev_ops_pci,
Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -56,7 +56,7 @@
old_debug = get_ehci_debug();
set_ehci_debug(0);
#endif
- pci_dev_set_resources(dev);
+ pci_set_resources(dev);
#ifdef CONFIG_USBDEBUG_DIRECT
res = find_resource(dev, 0x10);
Modified: coreboot-v3/southbridge/via/vt8237/ide.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/ide.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/via/vt8237/ide.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -99,7 +99,7 @@
.phase3_scan = 0,
//.phase4_enable_disable = vt8237_enable,
//.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_dev_set_resources,
+ //.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
};
Modified: coreboot-v3/southbridge/via/vt8237/lpc.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/lpc.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/via/vt8237/lpc.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -451,7 +451,7 @@
.phase2_fixup = vt8237_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vt8237_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = vt8237_enable_resources,
.phase6_init = vt8237r_init,
};
@@ -464,7 +464,7 @@
.phase2_fixup = vt8237_enable,
.phase3_scan = scan_static_bus,
.phase4_read_resources = vt8237_read_resources,
- .phase4_set_resources = pci_dev_set_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = vt8237_enable_resources,
.phase6_init = vt8237s_init,
};
Modified: coreboot-v3/southbridge/via/vt8237/sata.c
===================================================================
--- coreboot-v3/southbridge/via/vt8237/sata.c 2008-11-20 12:20:35 UTC (rev
1047)
+++ coreboot-v3/southbridge/via/vt8237/sata.c 2008-11-24 14:06:10 UTC (rev
1048)
@@ -103,7 +103,7 @@
.phase3_scan = 0,
//.phase4_enable_disable = vt8237_enable,
//.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_dev_set_resources,
+ //.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_i_init,
};
@@ -117,7 +117,7 @@
.phase3_scan = 0,
//.phase4_enable_disable = vt8237_enable,
//.phase4_read_resources = pci_dev_read_resources,
- //.phase4_set_resources = pci_dev_set_resources,
+ //.phase4_set_resources = pci_set_resources,
//.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_ii_init,
};
--
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