Author: stepan
Date: 2008-11-26 10:17:29 +0100 (Wed, 26 Nov 2008)
New Revision: 1059

Modified:
   coreboot-v3/arch/x86/intel/core2/stage0.S
Log:
back out until this issue is really fixed.
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Stefan Reinauer <[EMAIL PROTECTED]>



Modified: coreboot-v3/arch/x86/intel/core2/stage0.S
===================================================================
--- coreboot-v3/arch/x86/intel/core2/stage0.S   2008-11-26 02:16:37 UTC (rev 
1058)
+++ coreboot-v3/arch/x86/intel/core2/stage0.S   2008-11-26 09:17:29 UTC (rev 
1059)
@@ -3,7 +3,6 @@
  * 
  * Copyright (C) 2000,2007 Ronald G. Minnich <[EMAIL PROTECTED]>
  * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2008 Carl-Daniel Hailfinger
  * 
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -160,20 +159,9 @@
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
        movl    %eax, %esp
 
-       /* Store zero for the pointer to the global variables. */
-       pushl   $0
-
-       /* Restore the BIST result. */
+       /* Restore the BIST result */
        movl    %ebp, %eax
-
-       /* We need to set ebp? No need. */
        movl    %esp, %ebp
-
-       /* Second parameter: init_detected */
-       /* Store zero for the unused init_detected parameter. */
-       pushl   $0
-
-       /* First parameter: bist */
        pushl   %eax
 
 #if 0
@@ -182,7 +170,6 @@
 #endif
 
        call    stage1_phase1
-       /* We will not go back. */
 
        port80_post(0x2f)
 error:


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