Index: southbridge/via/vt8237/lpc.c =================================================================== --- southbridge/via/vt8237/lpc.c (revision 1061) +++ southbridge/via/vt8237/lpc.c (working copy) @@ -448,8 +448,8 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}}, .constructor = default_device_constructor, - .phase2_fixup = vt8237_enable, - .phase3_scan = scan_static_bus, + //.phase2_fixup = vt8237_enable, + //.phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = vt8237_enable_resources, @@ -462,7 +462,7 @@ .device = PCI_DEVICE_ID_VIA_VT8237S_LPC}}}, .constructor = default_device_constructor, .phase2_fixup = vt8237_enable, - .phase3_scan = scan_static_bus, + //.phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = vt8237_enable_resources, Index: southbridge/via/vt8237/ide.c =================================================================== --- southbridge/via/vt8237/ide.c (revision 1061) +++ southbridge/via/vt8237/ide.c (working copy) @@ -95,8 +95,8 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237_PATA}}}, .constructor = default_device_constructor, - .phase2_fixup = vt8237_enable, - .phase3_scan = 0, + //.phase2_fixup = vt8237_enable, + //.phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, //.phase4_read_resources = pci_dev_read_resources, //.phase4_set_resources = pci_set_resources, Index: southbridge/via/vt8237/stage1.c =================================================================== --- southbridge/via/vt8237/stage1.c (revision 1061) +++ southbridge/via/vt8237/stage1.c (working copy) @@ -28,6 +28,8 @@ #include #include "vt8237.h" +#define ANNOYING_SMBUS_MESSAGES 0 + /* TODO List: * * Merge the rest of the functions from v2, except smbus_fixup which doesn't * seem to be necessary any more (?) @@ -49,7 +51,7 @@ if ((host_status == 0x00 || host_status == 0x40 || host_status == 0x42) && (loops < SMBUS_TIMEOUT)) { - printk(BIOS_SPEW, "SMBus Ready/Completed Successfully\n"); + //printk(BIOS_SPEW, "SMBus Ready/Completed Successfully\n"); return; } if (loops >= SMBUS_TIMEOUT) @@ -61,7 +63,7 @@ if (host_status & (1 << 2)) printk(BIOS_ERR, "Device error\n"); if (host_status & (1 << 1)) - printk(BIOS_SPEW, "Interrupt/SMI# completed successfully\n"); + //printk(BIOS_SPEW, "Interrupt/SMI# completed successfully\n"); if (host_status & (1 << 0)) printk(BIOS_ERR, "Host busy\n"); } @@ -84,8 +86,6 @@ { int loops; - printk(BIOS_SPEW, "Waiting until SMBus ready\n"); - loops = 0; while ((inb(smbus_io_base + SMBHSTSTAT) & 1) == 1 && loops <= SMBUS_TIMEOUT) ++loops; @@ -104,9 +104,10 @@ { u8 val; +#if ANNOYING_SMBUS_MESSAGES printk(BIOS_SPEW, "SMBus Read from DIMM %d at address 0x%x\n", (int)dimm, offset); - +#endif smbus_reset(smbus_io_base); /* Clear host data port. */ @@ -128,8 +129,10 @@ smbus_wait_until_ready(smbus_io_base); val = inb(smbus_io_base + SMBHSTDAT0); +#if ANNOYING_SMBUS_MESSAGES printk(BIOS_SPEW, "Read: 0x%x\n", val); - +#endif + /* TODO: Is this necessary? */ smbus_reset(smbus_io_base); Index: southbridge/via/vt8237/sata.c =================================================================== --- southbridge/via/vt8237/sata.c (revision 1061) +++ southbridge/via/vt8237/sata.c (working copy) @@ -22,6 +22,7 @@ #include #include "vt8237.h" +#define pos(x) printk(BIOS_DEBUG, "At debug spot %d\n", x) /* TODO: use phase2_fixup to disable SATA */ static void sata_i_init(struct device *dev) { @@ -32,12 +33,16 @@ /* Class IDE Disk */ reg = pci_read_config8(dev, SATA_MISC_CTRL); reg &= 0x7f; /* Sub Class Write Protect off */ + pos(0); pci_write_config8(dev, SATA_MISC_CTRL, reg); - + pos(1); + /* Change the device class to SATA from RAID. */ pci_write_config8(dev, PCI_CLASS_DEVICE, 0x1); + pos(2); reg |= 0x80; /* Sub Class Write Protect on */ pci_write_config8(dev, SATA_MISC_CTRL, reg); + printk(BIOS_DEBUG, "Done SATA I init\n"); } /* VT8237R is SATA, VT8237S is SATAII */ @@ -93,6 +98,7 @@ reg |= 0x30; pci_write_config8(dev, 0x83, reg); } + printk(BIOS_DEBUG, "Done SATA II init\n"); } struct device_operations vt8237r_sata = { @@ -100,11 +106,11 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}}, .constructor = default_device_constructor, - .phase3_scan = 0, + //.phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, - //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_set_resources, - //.phase5_enable_resources = pci_dev_enable_resources, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_i_init, }; @@ -113,11 +119,10 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237S_SATA}}}, .constructor = default_device_constructor, - .phase2_fixup = 0, - .phase3_scan = 0, + //.phase3_scan = 0, //.phase4_enable_disable = vt8237_enable, - //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_set_resources, - //.phase5_enable_resources = pci_dev_enable_resources, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, .phase6_init = sata_ii_init, }; Index: southbridge/via/vt8237/vt8237.c =================================================================== --- southbridge/via/vt8237/vt8237.c (revision 1061) +++ southbridge/via/vt8237/vt8237.c (working copy) @@ -30,26 +30,36 @@ * VT8237R_SouthBridge_Revision2.06_Lead-Free.zip */ +const int d16_index[6] = {12, 13, 10, 8, 9, 7}; + +/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ void vt8237_enable(struct device *dev) { - struct device *lpc_dev; + u32 lpc_dev; u16 sb_fn_ctrl; - const u8 func = dev->path.pci.devfn & 0x7; - const u8 device = dev->path.pci.devfn >> 3; - const int d16_index[6] = {12, 13, 10, 8, 9, 7}; - + u8 func = dev->path.pci.devfn & 0x7; + u8 device = dev->path.pci.devfn >> 3; + u32 dev_bdf = PCI_BDF(0, device, func); printk(BIOS_DEBUG, "Enabling/Disabling device 0x%x function 0x%x.\n", device, func); - if(dev->id.pci.vendor != PCI_VENDOR_ID_VIA) + if (pci_conf1_read_config16(dev_bdf, PCI_VENDOR_ID) != PCI_VENDOR_ID_VIA) + { + printk(BIOS_DEBUG, "vt8237_enable ran for non-Via device!\n"); return; - - lpc_dev = dev_find_slot(0, PCI_BDF(0, 17, 0)); - sb_fn_ctrl = pci_read_config8(lpc_dev, 0x50) << 8; - sb_fn_ctrl |= pci_read_config8(lpc_dev, 0x51); + } + /* only dev 16 & 17 have disable-able functions */ + if (device |= 16 && device != 17) + return; + + lpc_dev = PCI_BDF(0, 17, 0); + sb_fn_ctrl = pci_conf1_read_config8(lpc_dev, 0x50) << 8; + sb_fn_ctrl |= pci_conf1_read_config8(lpc_dev, 0x51); + printk(BIOS_DEBUG, "Before enable/disable, sb_fn_ctrl 0x%x\n", sb_fn_ctrl); + if (device == 16) { /* If any port is enabled, the first port needs to be enabled */ @@ -76,9 +86,8 @@ sb_fn_ctrl |= (!dev->enabled << 15); } } - + + printk(BIOS_DEBUG, "After enable/disable, sb_fn_ctrl = 0x%x", sb_fn_ctrl); pci_write_config8(dev, 0x50, (sb_fn_ctrl >> 8) & 0xff); pci_write_config8(dev, 0x51, sb_fn_ctrl & 0xff); - - /* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */ } Index: include/arch/x86/mtrr.h =================================================================== --- include/arch/x86/mtrr.h (revision 1061) +++ include/arch/x86/mtrr.h (working copy) @@ -35,6 +35,7 @@ void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); +void early_mtrr_init(void); #endif Index: mainboard/jetway/j7f2/initram.c =================================================================== --- mainboard/jetway/j7f2/initram.c (revision 1061) +++ mainboard/jetway/j7f2/initram.c (working copy) @@ -39,67 +39,27 @@ return smbus_read_byte(dev, addr, SMBUS_IO_BASE); } -void find_smbus_devices(u8 min, u8 max) -{ - u8 dev; - u8 result; - for(dev = min; dev < max; dev++) - { - result = spd_read_byte(dev, SPD_MEMORY_TYPE); - switch(result) - { - case SPD_MEMORY_TYPE_SDRAM: printk(BIOS_DEBUG, - "Possible SDRAM spd at address 0x%2x\n", dev); - break; - case SPD_MEMORY_TYPE_SDRAM_DDR: printk(BIOS_DEBUG, - "Possible DDR SDRAM spd at address 0x%2x\n", dev); - break; - case SPD_MEMORY_TYPE_SDRAM_DDR2: printk(BIOS_DEBUG, - "Possible DDR2 SDRAM spd at address 0x%2x\n", dev); - break; - }; - } -} - - -void dump_smbus_registers(void) -{ - int device; - for(device = 1; device < (int)0x80; device++) { - int j; - //if(spd_read_byte(device, 0) < 0 ) - // continue; - printk(BIOS_DEBUG, "smbus: %02x", device); - for(j = 0; j < 256; j++) { - int status; - u8 byte; - status = spd_read_byte(device, j); - if (status < 0) { - break; - } - if ((j & 0xf) == 0) { - printk(BIOS_DEBUG, "\n%02x: ",j); - } - byte = status & 0xff; - printk(BIOS_DEBUG, "%02x ", byte); - } - printk(BIOS_DEBUG, "\n"); - } -} - static void enable_mainboard_devices(void) { + printk(BIOS_DEBUG, "In enable_mainboard_devices()\n"); u32 dev; + u8 reg8; - pci_conf1_find_device(0x1106, 0x3227, &dev); - /* Disable GP3 */ - pci_conf1_write_config8(dev, 0x98, 0x00); - - pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata - pci_conf1_write_config8(dev, 0x51, 0x1f); + //pci_conf1_find_device(0x1106, 0x3227, &dev); + dev = PCI_BDF(0, 17, 0); + printk(BIOS_DEBUG, "set dev=PCI_BDF(0,17,0)\n"); + reg8 = pci_conf1_read_config8(dev, 0x50); + printk(BIOS_DEBUG, "rx50 = 0x%x, setting to 0x%x\n", reg8, reg8 | 0x80); + pci_conf1_write_config8(dev, 0x50, reg8 | (1 << 7));//disable mc97 + printk(BIOS_DEBUG, "set rx50 done\n"); + reg8 = pci_conf1_read_config8(dev, 0x51); + printk(BIOS_DEBUG, "rx51 = 0x%x, setting to 0x%x\n", reg8, reg8 | 0x18); + pci_conf1_write_config8(dev, 0x51, reg8 | (1 << 4) | (1 << 3)); + printk(BIOS_DEBUG, "set rx51 done\n"); pci_conf1_write_config8(dev, 0x58, 0x60); pci_conf1_write_config8(dev, 0x59, 0x80); pci_conf1_write_config8(dev, 0x5b, 0x08); + printk(BIOS_DEBUG, "Done with lpc, moving to ide\n"); pci_conf1_find_device(0x1106, 0x0571, &dev); @@ -121,62 +81,69 @@ /* I'll be damned if I know what these do */ pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00 + printk(BIOS_DEBUG, "done enable_mainboard_devices\n"); } -static void enable_shadow_ram(void) +static void enable_shadow_ram(struct board_info *dev) { u8 shadowreg; printk(BIOS_DEBUG, "Enabling shadow ram\n"); /* Enable shadow ram as normal dram */ /* 0xc0000-0xcffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff); + pci_conf1_write_config8(dev->d0f3, 0x80, 0xff); + pci_conf1_write_config8(dev->d0f7, 0x61, 0xff); /* 0xd0000-0xdffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff); + pci_conf1_write_config8(dev->d0f3, 0x81, 0xff); + pci_conf1_write_config8(dev->d0f7, 0x62, 0xff); /* 0xe0000-0xeffff */ - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff); + pci_conf1_write_config8(dev->d0f3, 0x82, 0xff); + pci_conf1_write_config8(dev->d0f7, 0x64, 0xff); /* 0xf0000-0xfffff */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83); + shadowreg = pci_conf1_read_config8(dev->d0f3, 0x83); shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg); + pci_conf1_write_config8(dev->d0f3, 0x83, shadowreg); /* Do it again for the vlink controller */ - shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63); + shadowreg = pci_conf1_read_config8(dev->d0f7, 0x63); shadowreg |= 0x30; - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg); + pci_conf1_write_config8(dev->d0f7, 0x63, shadowreg); } -static void enable_vlink(void) +/* TODO: PCI_BDF -> dev->d0f7 */ +static void enable_vlink(struct board_info *dev) { printk(BIOS_DEBUG, "Enabling Via V-Link\n"); - +#if 0 /* Enable V-Link statically in 8x mode, using Jetway default values */ //40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01 - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04); - //pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01); + pci_conf1_write_config8(dev->d0f7, 0x42, 0x88); + pci_conf1_write_config8(dev->d0f7, 0x45, 0x44); + pci_conf1_write_config8(dev->d0f7, 0x46, 0x00); + pci_conf1_write_config8(dev->d0f7, 0x47, 0x04); + //pci_conf1_write_config8(dev->d0f7, 0x48, 0x13); + pci_conf1_write_config8(dev->d0f7, 0x4b, 0x80); + pci_conf1_write_config8(dev->d0f7, 0x4c, 0x82); + pci_conf1_write_config8(dev->d0f7, 0x4d, 0x44); + pci_conf1_write_config8(dev->d0f7, 0x4e, 0x00); + pci_conf1_write_config8(dev->d0f7, 0x4f, 0x01); //b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00 - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98); - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77); + pci_conf1_write_config8(dev->d0f7, 0xb4, 0x35); + pci_conf1_write_config8(dev->d0f7, 0xb5, 0x66); + pci_conf1_write_config8(dev->d0f7, 0xb6, 0x66); + pci_conf1_write_config8(dev->d0f7, 0xb7, 0x64); + pci_conf1_write_config8(dev->d0f7, 0xb8, 0x45); + pci_conf1_write_config8(dev->d0f7, 0xb9, 0x98); + pci_conf1_write_config8(dev->d0f7, 0xba, 0x77); /* This has to be done last, I think */ - pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13); + pci_conf1_write_config8(dev->d0f7, 0x48, 0x13); +#endif + + /* Thanks to Urbez Santana Roma for this */ + pci_conf1_write_config8(dev->d1f0, 0x19, 0x1); + pci_conf1_write_config8(dev->d1f0, 0x1a, 0x1); } int main(void) @@ -194,14 +161,13 @@ printk(BIOS_DEBUG, "In initram.c main()\n"); - enable_vlink(); + c7_cpu_setup(ctrl->d0f2); + + enable_vlink(ctrl); enable_mainboard_devices(); - enable_shadow_ram(); + //enable_shadow_ram(ctrl); - c7_cpu_setup(PCI_BDF(0, 0, 2)); - enable_smbus(SMBUS_IO_BASE); - //find_smbus_devices(0x00, 0xff); sdram_set_registers(ctrl); sdram_set_spd_registers(ctrl); ddr2_sdram_enable(ctrl); Index: mainboard/jetway/j7f2/stage1.c =================================================================== --- mainboard/jetway/j7f2/stage1.c (revision 1061) +++ mainboard/jetway/j7f2/stage1.c (working copy) @@ -22,7 +22,9 @@ #include #include #include +#include #include +#include #include #include #include @@ -32,20 +34,21 @@ { u32 dev; + /* Breaks booting! */ + //early_mtrr_init(); + post_code(POST_START_OF_MAIN); f71805f_enable_serial(0x2e); /* Enable multifunction for northbridge. */ pci_conf1_write_config8(0x00, 0x4f, 0x01); printk(BIOS_SPEW, "In hardware_stage1()\n"); /* Disabled GP3, to keep the system from rebooting automatically */ - //pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev); dev = PCI_BDF(0, 17, 0); pci_conf1_write_config8(dev, 0x98, 0x00); } void mainboard_pre_payload(void) { - //banner(BIOS_DEBUG, "mainboard_pre_payload: done"); } Index: mainboard/jetway/j7f2/Makefile =================================================================== --- mainboard/jetway/j7f2/Makefile (revision 1061) +++ mainboard/jetway/j7f2/Makefile (working copy) @@ -20,8 +20,8 @@ ## TODO -STAGE0_MAINBOARD_SRC := $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ - $(src)/arch/x86/stage1_mtrr.c +STAGE0_MAINBOARD_SRC := $(src)/arch/x86/stage1_mtrr.c \ + $(src)/mainboard/$(MAINBOARDDIR)/stage1.c INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/via/cn700/initram.c \