This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Read children's resources when yours are read.
3. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/domain.c:
A comment for later cleanup efforts.
Change the resource base from 0x400 to 0x1000 to match the granularity.
Add the IORESOURCE_BRIDGE flag.
Read the resources of the grandchildren.
This should disappear when the domain has the children.
Update k8_pci_domain_set_resources:
1. remove compute_allocate_resource call
2. Change phase4_assign_resources to phase4_set_resources
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Make the VGA resource remain visible.
Stop passing around nodeid so much.
Remove unneeded #defines
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
northbridge/intel/i440bxemulation/i440bx.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Thanks,
Myles
Index: svn/northbridge/amd/k8/domain.c
===================================================================
--- svn.orig/northbridge/amd/k8/domain.c
+++ svn/northbridge/amd/k8/domain.c
@@ -106,6 +106,7 @@ static void k8_pci_domain_read_resources
u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x04);
+ /* At this point we don't need to use this*/
/* Is this register allocated? */
if ((base & 3) != 0) {
unsigned nodeid, link;
@@ -123,42 +124,53 @@ static void k8_pci_domain_read_resources
}
}
}
-#ifndef CONFIG_PCI_64BIT_PREF_MEM
- /* Initialize the system-wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->base = 0x400;
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- /* Initialize the system-wide memory resource constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-#else
- /* Initialize the system-wide io space constraints */
+ /* Initialize the domain io space constraints */
resource = new_resource(dev, 0);
- resource->base = 0x400;
+ resource->base = 0x1000;
+ resource->align = log2c(HT_IO_HOST_ALIGN);
+ resource->gran = log2c(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_IO, IORESOURCE_IO);
+ resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
- /* Initialize the system-wide prefetchable memory resource constraints */
+ /* Initialize the domain prefetchable memory resource constraints */
resource = new_resource(dev, 1);
+ resource->align = log2c(HT_MEM_HOST_ALIGN);
+ resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM | IORESOURCE_PREFETCH);
+ resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_BRIDGE;
- /* Initialize the system-wide memory resource constraints */
+ /* Initialize the domain memory resource constraints */
resource = new_resource(dev, 2);
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
-#endif
+ resource->align = log2c(HT_MEM_HOST_ALIGN);
+ resource->gran = log2c(HT_MEM_HOST_ALIGN);
+ resource->limit = 0xfcffffffULL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
+
+ { /* make this self contained so it can disappear later. */
+unsigned link;
+struct device *child, *gchild;
+for ( link=0; link < dev->links; link++) {
+ for (child = dev->link[link].children; child; child = child->sibling) {
+
+ if (child && child->ops &&
+ child->ops->phase4_read_resources)
+ child->ops->phase4_read_resources(child);
+ else
+ printk(BIOS_ERR,"domain link %d child (%s) missing read_resources!\n", link, child->dtsname);
+ /* This is needed because k8 device shouldn't have children. Only the
+ * k8 domain should. Fix this in the DTS!
+ */
+ for (gchild = child->link[0].children; gchild; gchild = gchild->sibling) {
+ if (gchild && gchild->ops &&
+ gchild->ops->phase4_read_resources)
+ gchild->ops->phase4_read_resources(gchild);
+ }
+
+ } /* for*/
+}
+ } /* self contained */
+
printk(BIOS_DEBUG, "k8_pci_domain_read_resources done\n");
}
@@ -234,15 +246,8 @@ static void k8_pci_domain_set_resources(
last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++)
{
-#if 1
- resource->flags |= IORESOURCE_ASSIGNED;
- resource->flags &= ~IORESOURCE_STORED;
-#endif
- compute_allocate_resource(&dev->link[0], resource,
- BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
resource->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, resource, "");
+ report_resource_stored(dev, resource, __func__);
}
#endif
@@ -360,7 +365,7 @@ static void k8_pci_domain_set_resources(
k8_ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
}
- phase4_assign_resources(&dev->link[0]);
+ phase4_set_resources(&dev->link[0]);
}
static unsigned int k8_domain_scan_bus(struct device * dev, unsigned int max)
Index: svn/northbridge/amd/k8/pci.c
===================================================================
--- svn.orig/northbridge/amd/k8/pci.c
+++ svn/northbridge/amd/k8/pci.c
@@ -261,7 +261,7 @@ static int reg_useable(unsigned reg,
{
struct resource *res = NULL;
struct device *dev = NULL;
- unsigned nodeid = 0, link = 0;
+ unsigned link = 0;
int result;
/* Look for the resource that matches this register. */
@@ -270,7 +270,6 @@ static int reg_useable(unsigned reg,
for (link = 0; !res && (link < 3); link++) {
res = probe_resource(dev, 0x100 + (reg | link));
}
- nodeid++;
}
/* If no allocated resource was found, it is free - return 2 */
@@ -279,7 +278,7 @@ static int reg_useable(unsigned reg,
result = 0;
/* If the resource is allocated to the link and node already */
if ((goal_link == (link - 1)) &&
- (goal_nodeid == (nodeid - 1)) && (res->flags <= 1)) {
+ (goal_nodeid == amdk8_nodeid(dev)) && (res->flags <= 1)) {
result = 1;
}
}
@@ -354,9 +353,7 @@ static void amdk8_link_read_bases(struct
resource->align = log2c(HT_IO_HOST_ALIGN);
resource->gran = log2c(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_IO, IORESOURCE_IO);
+ resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
}
/* Initialize the prefetchable memory constraints on the current bus */
@@ -367,10 +364,8 @@ static void amdk8_link_read_bases(struct
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM | IORESOURCE_PREFETCH);
+ resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
+ IORESOURCE_BRIDGE;
}
/* Initialize the memory constraints on the current bus */
@@ -381,17 +376,15 @@ static void amdk8_link_read_bases(struct
resource->align = log2c(HT_MEM_HOST_ALIGN);
resource->gran = log2c(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
- resource->flags = IORESOURCE_MEM;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
+ resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
}
}
static void amdk8_read_resources(struct device *dev)
{
- printk(BIOS_DEBUG, "amdk8_read_resources\n");
+ printk(BIOS_DEBUG, "amdk8_read_resources node %s\n", dev->dtsname );
unsigned nodeid, link;
+
nodeid = amdk8_nodeid(dev);
for (link = 0; link < dev->links; link++) {
@@ -404,12 +397,13 @@ static void amdk8_read_resources(struct
printk(BIOS_DEBUG, "amdk8_read_resources done\n");
}
-static void amdk8_set_resource(struct device *dev, struct resource *resource,
- unsigned nodeid)
+static void amdk8_set_resource(struct device *dev, struct resource *resource)
{
resource_t rbase, rend;
unsigned reg, link;
char buf[50];
+ unsigned nodeid;
+
printk(BIOS_DEBUG, "amdk8_set_resource\n");
/* Make certain the resource has actually been set */
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
@@ -438,11 +432,10 @@ static void amdk8_set_resource(struct de
/* Get the register and link */
reg = resource->index & 0xfc;
link = resource->index & 3;
+ nodeid = amdk8_nodeid(dev);
if (resource->flags & IORESOURCE_IO) {
u32 base, limit;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_IO, IORESOURCE_IO);
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc;
@@ -467,11 +460,6 @@ static void amdk8_set_resource(struct de
f1_write_config32(reg, base);
} else if (resource->flags & IORESOURCE_MEM) {
u32 base, limit;
- compute_allocate_resource(&dev->link[link], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- resource->
- flags & (IORESOURCE_MEM |
- IORESOURCE_PREFETCH));
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
@@ -498,12 +486,13 @@ static void amdk8_set_resource(struct de
extern struct device *vga_pri; // the primary vga device, defined in device.c
#endif
-static void amdk8_create_vga_resource(struct device *dev, unsigned nodeid)
+static void amdk8_create_vga_resource(struct device *dev)
{
struct resource *resource;
unsigned link;
u32 base, limit;
unsigned reg;
+ unsigned nodeid = amdk8_nodeid(dev);
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
@@ -557,33 +546,24 @@ static void amdk8_create_vga_resource(st
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
- /* release the temp resource */
- resource->flags = 0;
+ /* Don't release the temp resource */
+ resource->flags |= IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ printk(BIOS_DEBUG, "VGA: used k8 reg %02lx\n", resource->index);
}
static void amdk8_set_resources(struct device *dev)
{
- unsigned nodeid, link;
int i;
- /* Find the nodeid */
- nodeid = amdk8_nodeid(dev);
-
- printk(BIOS_DEBUG, "amdk8_set_resources: nodeid %d\n", nodeid);
- amdk8_create_vga_resource(dev, nodeid);
+ printk(BIOS_DEBUG, "amdk8_set_resources: %s\n", dev->dtsname);
+ amdk8_create_vga_resource(dev);
/* Set each resource we have found */
for (i = 0; i < dev->resources; i++) {
- amdk8_set_resource(dev, &dev->resource[i], nodeid);
+ amdk8_set_resource(dev, &dev->resource[i]);
}
- for (link = 0; link < dev->links; link++) {
- struct bus *bus;
- bus = &dev->link[link];
- if (bus->children) {
- phase4_assign_resources(bus);
- }
- }
+ phase4_set_resources(&dev->link[0]);
}
static void amdk8_enable_resources(struct device *dev)
@@ -600,10 +580,6 @@ static void mcf0_control_init(struct dev
printk(BIOS_DEBUG, "done.\n");
}
-#ifdef CONFIG_PCI_64BIT_PREF_MEM
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
-#endif
-
struct device_operations k8_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
Index: svn/southbridge/amd/amd8132/amd8132_bridge.c
===================================================================
--- svn.orig/southbridge/amd/amd8132/amd8132_bridge.c
+++ svn/southbridge/amd/amd8132/amd8132_bridge.c
@@ -31,8 +31,13 @@
#define NMI_OFF 0
-#define NPUML 0xD9 /* Non prefetchable upper memory limit */
-#define NPUMB 0xD8 /* Non prefetchable upper memory base */
+/* We don't implement this because:
+ * 1. There's only one pair of registers for both devices.
+ * - This breaks our model for resource allocation.
+ * 2. The datasheet recommends against it.
+ */
+/* #define NPUML 0xD9 Non prefetchable upper memory limit */
+/* #define NPUMB 0xD8 Non prefetchable upper memory base */
static void amd8132_walk_children(struct bus *bus,
void (*visit)(struct device * dev, void *ptr), void *ptr)
@@ -165,6 +170,7 @@ static unsigned int amd8132_scan_bus(str
info.master_devices = 0;
amd8132_walk_children(bus, amd8132_count_dev, &info);
+#warning Bus disabling disabled for amd8132
#if 0
/* Disable the bus if there are no devices on it
*/
@@ -309,40 +315,6 @@ static void amd8132_pcix_init(struct dev
return;
}
-static void bridge_read_resources(struct device *dev)
-{
- struct resource *res;
- pci_bus_read_resources(dev);
- res = probe_resource(dev, PCI_MEMORY_BASE);
- if (res) {
- res->limit = 0xffffffffffULL;
- }
-}
-
-static void bridge_set_resources(struct device *dev)
-{
- struct resource *res;
- res = find_resource(dev, PCI_MEMORY_BASE);
- if (res) {
- resource_t base, end;
- /* set the memory range */
- dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
- res->flags |= IORESOURCE_STORED;
- compute_allocate_resource(&dev->link[0], res,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
- base = res->base;
- end = resource_end(res);
- pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
- pci_write_config8(dev, NPUML, (base >> 32) & 0xff);
- pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
- pci_write_config8(dev, NPUMB, (end >> 32) & 0xff);
-
- report_resource_stored(dev, res, "including NPUML");
- }
- pci_set_resources(dev);
-}
-
struct device_operations amd8132_pcix = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_AMD,
@@ -350,8 +322,8 @@ struct device_operations amd8132_pcix =
.constructor = default_device_constructor,
.reset_bus = pci_bus_reset,
.phase3_scan = amd8132_scan_bridge,
- .phase4_read_resources = bridge_read_resources,
- .phase4_set_resources = bridge_set_resources,
+ .phase4_read_resources = pci_bus_read_resources,
+ .phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = amd8132_pcix_init,
.ops_pci = &pci_bus_ops_pci,
Index: svn/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- svn.orig/northbridge/intel/i440bxemulation/i440bx.c
+++ svn/northbridge/intel/i440bxemulation/i440bx.c
@@ -80,7 +80,7 @@ static void pci_domain_set_resources(str
/* 768 kB .. Systop (in KB) */
ram_resource(dev, idx++, 768, tolmk - 768);
}
- phase4_assign_resources(&dev->link[0]);
+ phase4_set_resources(&dev->link[0]);
}
/* Here are the operations for when the northbridge is running a PCI domain. */
--
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