Author: stuge
Date: 2008-12-03 22:24:40 +0100 (Wed, 03 Dec 2008)
New Revision: 3790

Modified:
   trunk/util/flashrom/Makefile
   trunk/util/flashrom/chipset_enable.c
   trunk/util/flashrom/flash.h
   trunk/util/flashrom/flashrom.c
Log:
Replace #ifdefs for sc520 systems by run time probing.

fixes #109

Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>


Modified: trunk/util/flashrom/Makefile
===================================================================
--- trunk/util/flashrom/Makefile        2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/Makefile        2008-12-03 21:24:40 UTC (rev 3790)
@@ -11,7 +11,7 @@
 INSTALL = /usr/bin/install
 PREFIX  = /usr/local
 #CFLAGS  = -O2 -g -Wall -Werror
-CFLAGS  = -Os -Wall -Werror # -DTS5300
+CFLAGS  = -Os -Wall -Werror
 OS_ARCH        = $(shell uname)
 ifeq ($(OS_ARCH), SunOS)
 LDFLAGS = -lpci -lz

Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c        2008-12-02 12:26:17 UTC (rev 
3789)
+++ trunk/util/flashrom/chipset_enable.c        2008-12-03 21:24:40 UTC (rev 
3790)
@@ -35,6 +35,8 @@
 #include <unistd.h>
 #include "flash.h"
 
+unsigned long flashbase = 0;
+
 /**
  * flashrom defaults to LPC flash devices. If a known SPI controller is found
  * and the SPI strappings are set, this will be overwritten by the probing 
code.
@@ -797,6 +799,59 @@
        return 0;
 }
 
+/**
+ * Usually on the x86 architectures (and on other PC-like platforms like some
+ * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
+ * Elan SC520 only a small piece of the system flash is mapped there, but the
+ * complete flash is mapped somewhere below 1G. The position can be determined
+ * by the BOOTCS PAR register.
+ */
+static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
+{
+       int i, bootcs_found = 0;
+       uint32_t parx = 0;
+       void *mmcr;
+
+       /* 1. Map MMCR */
+       mmcr = mmap(0, getpagesize(), PROT_WRITE | PROT_READ,
+                       MAP_SHARED, fd_mem, (off_t)0xFFFEF000);
+
+       if (mmcr == MAP_FAILED) {
+               perror("Can't mmap Elan SC520 specific registers using " 
MEM_DEV);
+               exit(1);
+       }
+
+       /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
+        *    BOOTCS region (PARx[31:29] = 100b)e
+        */
+       for (i = 0x88; i <= 0xc4; i += 4) {
+               parx = *(volatile uint32_t *)(mmcr + i);
+               if ((parx >> 29) == 4) {
+                       bootcs_found = 1;
+                       break; /* BOOTCS found */
+               }
+       }
+
+       /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
+        *    PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
+        */
+       if (bootcs_found) {
+               if (parx & (1 << 25)) {
+                       parx &= (1 << 14) - 1; /* Mask [13:0] */
+                       flashbase = parx << 16;
+               } else {
+                       parx &= (1 << 18) - 1; /* Mask [17:0] */
+                       flashbase = parx << 12;
+               }
+       } else {
+               printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash 
at 4G\n");
+       }
+
+       /* 4. Clean up */
+       munmap (mmcr, getpagesize());
+       return 0;
+}
+
 typedef struct penable {
        uint16_t vendor, device;
        const char *name;
@@ -875,6 +930,7 @@
        {0x10de, 0x0548, "NVIDIA MCP67",        enable_flash_mcp55},
        {0x1002, 0x4377, "ATI SB400",           enable_flash_sb400},
        {0x1166, 0x0205, "Broadcom HT-1000",    enable_flash_ht1000},
+       {0x1022, 0x3000, "AMD Elan SC520",      get_flashbase_sc520},
 };
 
 void print_supported_chipsets(void)

Modified: trunk/util/flashrom/flash.h
===================================================================
--- trunk/util/flashrom/flash.h 2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/flash.h 2008-12-03 21:24:40 UTC (rev 3790)
@@ -410,6 +410,8 @@
 int chipset_flash_enable(void);
 void print_supported_chipsets(void);
 
+extern unsigned long flashbase;
+
 typedef enum {
        BUS_TYPE_LPC,
        BUS_TYPE_ICH7_SPI,

Modified: trunk/util/flashrom/flashrom.c
===================================================================
--- trunk/util/flashrom/flashrom.c      2008-12-02 12:26:17 UTC (rev 3789)
+++ trunk/util/flashrom/flashrom.c      2008-12-03 21:24:40 UTC (rev 3790)
@@ -105,7 +105,7 @@
 {
        volatile uint8_t *bios;
        struct flashchip *flash;
-       unsigned long flash_baseaddr = 0, size;
+       unsigned long size;
 
        for (flash = first_flash; flash && flash->name; flash++) {
                if (chip_to_probe && strcmp(flash->name, chip_to_probe) != 0)
@@ -133,16 +133,11 @@
                         */
                        size = getpagesize();
                }
-#ifdef TS5300
-               // FIXME: Wrong place for this decision
-               // FIXME: This should be autodetected. It is trivial.
-               flash_baseaddr = 0x9400000;
-#else
-               flash_baseaddr = (0xffffffff - size + 1);
-#endif
+               if (!flashbase)
+                       flashbase = (0xffffffff - size + 1);
 
                bios = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
-                           fd_mem, (off_t) flash_baseaddr);
+                           fd_mem, (off_t) flashbase);
                if (bios == MAP_FAILED) {
                        perror("Can't mmap memory using " MEM_DEV);
                        exit(1);
@@ -167,7 +162,7 @@
                return NULL;
 
        printf("Found chip \"%s %s\" (%d KB) at physical address 0x%lx.\n",
-              flash->vendor, flash->name, flash->total_size, flash_baseaddr);
+              flash->vendor, flash->name, flash->total_size, flashbase);
        return flash;
 }
 


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