-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all,
I finally got the powernow working after countless hours. And CPU runs fullspeed after power up! The patch changes the LDTSTOP length as well mostly default content of 0xec, 0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong. Furthermore this fix for powernow may not work on CPUs hit by errata #181. Workaround should be implemented. The powernow may not work on pre-A2 revisions of VT8237S silicon, revision reg is unknown. Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkk4ZfwACgkQ3J9wPJqZRNXv6QCeLPi9cX3OM9v/V/RoABUUJNcL txkAn1nz4yCEQyFZC6quJ1GwvUStmozQ =UKX4 -----END PGP SIGNATURE-----
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c (revision 3794)
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c (working copy)
@@ -236,20 +236,10 @@
devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);
+
if (devctl == PCI_DEV_INVALID)
return;
- /* TODO: Why is this an extra block? */
- {
- u8 tmp;
- tmp = pci_read_config8(devctl, 0xec);
- print_debug("EC is ");
- print_debug_hex8(tmp);
- print_debug(" E5 is ");
- tmp = pci_read_config8(dev, 0xe5);
- print_debug_hex8(tmp);
- }
-
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);
@@ -261,47 +251,15 @@
* Will work for C3 and for FID/VID change.
*/
- /* FIXME */
- outb(0xff, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
-// outb(0x4, VT8237R_ACPI_IO_BASE + 0x50); /* Maybe unneeded? */
+ outb(0xff, VT8237R_ACPI_IO_BASE + 0x50);
- /* It seems for AMD LDTSTP is connected not to SLP anymore. */
- /* Enable 0: DPSLP# / DPRSTP# / VRDSLP */
-
- /*
- * Enable SATA LED, VR timer = 100us.
- * Enable DPSLP# / DPRSTP# / VRDSLP - WARNING LDTSTP connetcs
- * to some of those pins! (and not to SLP as on R ver).
- */
- pci_write_config8(dev, 0xe5, 0x69); /* FIXME */
-
- /*
- * REQ5 as PCI request input - should be together with
- * INTE-INTH. Fast VR timer disable - need for LDTSTP signal.
- */
- pci_write_config8(dev, 0xe4, 0xa5);
-
/* Reduce further the STPCLK/LDTSTP signal to 5us. */
pci_write_config8(dev, 0xec, 0x4);
- /* Host Bus Power Management Control, maybe not needed. */
- pci_write_config8(dev, 0x8c, 0x5);
-
/* So the chip knows we are on AMD. */
- pci_write_config8(devctl, 0x7c, 0x77);
+ pci_write_config8(devctl, 0x7c, 0x7f);
- devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- 0x2336), 0);
- if (devctl == PCI_DEV_INVALID)
- return;
-
- /*
- * Enable C2NOW delay to PSTATECTL VID / FID Change Delay
- * to P-State Control.
- */
- pci_write_config8(devctl, 0xa6, 0x83);
-
- // return; // FIXME: Fall through some revs have it old way.
+ return;
}
/* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c (revision 3794)
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c (working copy)
@@ -264,14 +264,10 @@
pci_write_config32(dev, 0xbc,
(VT8237S_SPI_MEM_BASE >> 8) | (tmp & 0xFF000000));
- /* Enable SATA LED, VR timer = 100us, VR timer should be fixed. */
- pci_write_config8(dev, 0xe5, 0x69);
-
/*
* REQ5 as PCI request input - should be together with INTE-INTH.
- * Fast VR timer disable - need for LDTSTOP_L signal.
*/
- pci_write_config8(dev, 0xe4, 0xa5);
+ pci_write_config8(dev, 0xe4, 0x04);
/* Reduce further the STPCLK/LDTSTP signal to 5us. */
pci_write_config8(dev, 0xec, 0x4);
Index: src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c (revision 3794)
+++ src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c (working copy)
#include "cpu/amd/car/copy_and_run.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
+
+#define SB_VFSMAF 0
+
+/* this function might fail on some K8 CPUs with errata #181 */
+static void ldtstop_sb(void)
+{
+ print_debug("toggle LDTSTP#\r\n");
+ u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
+ reg = reg ^ (1 << 0);
+ outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
+ reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
+ print_debug("done\r\n");
+}
+
+
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/resourcemap.c"
@@ -282,7 +299,7 @@
print_debug("after enable_fid_change\r\n");
/* FIXME does not work yet */
-// init_fidvid_bsp(bsp_apicid);
+ init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
allow_all_aps_stop(bsp_apicid);
fix_powernow.patch.sig
Description: Binary data
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