On 05.12.2008 22:17, ron minnich wrote: > Add support for creating an smm top-level object. > > Whether SMM is added or not depends on the mainboard. To enable SMM, > the Kconfig variable SMM should be set, and the SMM variable should be > defined in the mainbard. > > Also correct a type CONFIG_HPET should be HPET. > > Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> > > Index: mainboard/kontron/Kconfig > =================================================================== > --- mainboard/kontron/Kconfig (revision 1064) > +++ mainboard/kontron/Kconfig (working copy) > @@ -32,6 +32,7 @@ > select SOUTHBRIDGE_INTEL_I82801GX > select SUPERIO_WINBOND_W83627THG > select PIRQ_TABLE > + select SMM > help > Kontron 986LCD-M Series mainboards > > Index: mainboard/kontron/986lcd-m/mainboard.h > =================================================================== > --- mainboard/kontron/986lcd-m/mainboard.h (revision 1064) > +++ mainboard/kontron/986lcd-m/mainboard.h (working copy) > @@ -31,3 +31,5 @@ > /* nowhere else to go yet */ > #define TEST_SMM_FLASH_LOCKDOWN 0 > > +#define TTYS0_BASE 0x3f8 > + > Index: mainboard/kontron/986lcd-m/Makefile > =================================================================== > --- mainboard/kontron/986lcd-m/Makefile (revision 1064) > +++ mainboard/kontron/986lcd-m/Makefile (working copy) > @@ -35,3 +35,4 @@ > $(Q)printf " BUILD DUMMY VPD\n" > $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) > > +SMM=$(obj)/southbridge/intel/i82801gx/smm.elf
Hm. Here you use the = operator. > Index: arch/x86/Kconfig > =================================================================== > --- arch/x86/Kconfig (revision 1064) > +++ arch/x86/Kconfig (working copy) > @@ -72,13 +72,21 @@ > arch/x86/Makefile for more hints on possible values. > It is usually set in mainboard/*/Kconfig. > > -config CONFIG_HPET > +config HPET > boolean > depends CPU_AMD_K8 > help > Whether to configure a High Precision Event Timer (HPET). Note that > HPETs are known to be bug-prone. > > +config SMM > + boolean > + help > + Whether to configure System Management Mode support. > + This is mainboard-enabled. This is a tricky option that > + should not be enabled/disabled casually, as some chipsets > + will not work without some form of SMM enabled. > + > config K8_REV_F_SUPPORT > hex > default 0 if CPU_AMD_K8 > Index: arch/x86/Makefile > =================================================================== > --- arch/x86/Makefile (revision 1064) > +++ arch/x86/Makefile (working copy) > @@ -48,7 +48,7 @@ > COMPRESSFLAG := -C nrv2b > endif > > -$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock > $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 > $(obj)/option_table > +$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock > $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 > $(obj)/option_table $(SMM) > $(Q)printf " LAR $(subst $(shell pwd)/,,$(@))\n" > $(Q)rm -f $(obj)/coreboot.rom > $(Q)cd $(obj) && \ > @@ -74,6 +74,10 @@ > $(Q)printf " ZEROING lar -z ./coreboot.rom\n" > $(Q)cd $(obj) && ./util/lar/lar -z ./coreboot.rom > endif > +ifeq ($(CONFIG_SMM),y) > + $(Q)printf " Adding smm.elf\n" > + $(Q)cd $(obj) && ./util/lar/lar -e $(COMPRESSFLAG) -a > $(obj)/coreboot.rom $(SMM):normal/smm; > +endif > $(Q)# QEMU wants bios.bin: > $(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero". > $(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/bios.bin)\n" > Index: Makefile > =================================================================== > --- Makefile (revision 1064) > +++ Makefile (working copy) > @@ -109,6 +109,9 @@ > # the compiler actually used for the build (e.g. on cross compiler setups). > CFLAGS += -nostdinc -isystem `$(CC) -print-file-name=include` > > +# Optional SMM > +SMM= Same here. > + > include lib/Makefile > include device/Makefile > include mainboard/$(MAINBOARDDIR)/Makefile > > If you explain or change the makefile hunks I commented on, the patch is Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
