Author: stepan
Date: 2008-12-05 23:38:18 +0100 (Fri, 05 Dec 2008)
New Revision: 3802
Modified:
trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
Log:
Fixes to AMD MCT code, found by Marco Schmidt <[EMAIL PROTECTED]>
Signed-off-by: Stefan Reinauer <[EMAIL PROTECTED]>
Acked-by: Marc Jones <[EMAIL PROTECTED]>
Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-12-05
18:38:57 UTC (rev 3801)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c 2008-12-05
22:38:18 UTC (rev 3802)
@@ -3400,6 +3400,8 @@
u8 max_dimms;
// FIXME: skip for Ax
+
+ dev = pDCTstat->dev_dct;
/* Tri-state unused ODTs when motherboard termination is available */
max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
Modified: trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
2008-12-05 18:38:57 UTC (rev 3801)
+++ trunk/coreboot-v2/src/northbridge/amd/amdmct/wrappers/mcti_d.c
2008-12-05 22:38:18 UTC (rev 3802)
@@ -197,13 +197,16 @@
case NV_CS_SpareCTL:
val = 0; /* Disabled */
//val = 1; /* Enabled */
+ break;
case NV_SyncOnUnEccEn:
val = 0; /* Disabled */
//val = 1; /* Enabled */
+ break;
case NV_Unganged:
/* channel interleave is better performance than ganged mode at
this time */
val = 1; /* Enabled */
//val = 0; /* Disabled */
+ break;
case NV_ChannelIntlv:
val = 5; /* Not currently checked in mctchi_d.c */
/* Bit 0 = 0 - Disable
@@ -213,7 +216,7 @@
* 10b - Hash*, XOR of address bits [20:16, 6]
* 11b - Hash*, XOR of address bits [20:16, 9]
*/
-
+ break;
}
return val;
--
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