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Hash: SHA1
Hello,
I started to hack to make SeaBIOS boot Windows XP and of course its installer.
The patch attached fixes some stuff already noticed by Kevin (FACP align, wrong
total size). And it adds some dynamic _CRS calculation in AML code. It uses SSDT
table with IO resources. For some reason this does not work, but resource hack
allows to boot Windows ACPI hal installer. I won't have much time to continue
with this week or so (maybe more...).
The idea is to let the PCI CRS resource to be calculated dynamically. The CRS
resource for host bridge is needed for Windows. Some ideas are described here:
http://www.acpi.info/acpi_faq.htm How is it done? Coreboot amd-acpi.c reads all
IO resource registers and put them into SSDT table. The AML code in
amdk8_util.asl should construct the IO resource containers which will be
returned concatenated with BUF0. As I stated above, it ends with 0xA5 STOP.
There is some problem somewhere, but once it is fixed, windows should work ;)
Rudolf
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Index: src/cpu/amd/model_fxx/model_fxx_init.c
===================================================================
--- src/cpu/amd/model_fxx/model_fxx_init.c (revision 3805)
+++ src/cpu/amd/model_fxx/model_fxx_init.c (working copy)
@@ -512,9 +512,9 @@
k8_errata();
/* Set SMMLOCK to avoid exploits messing with SMM */
- msr = rdmsr(HWCR_MSR);
- msr.lo |= (1 << 0);
- wrmsr(HWCR_MSR, msr);
+// msr = rdmsr(HWCR_MSR);
+// msr.lo |= (1 << 0);
+// wrmsr(HWCR_MSR, msr);
/* Set the processor name string */
init_processor_name();
Index: src/mainboard/asus/m2v-mx_se/fadt.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/fadt.c (revision 3805)
+++ src/mainboard/asus/m2v-mx_se/fadt.c (working copy)
@@ -75,10 +75,10 @@
fadt->day_alrm = 0x7d;
fadt->mon_alrm = 0x7e;
fadt->century = 0x32;
- /* fixme 5 - 10 */
- fadt->iapc_boot_arch = 0x1;
+ /* We have legacy devices, 8042, VGA is ok to probe, MSI are not supported */
+ fadt->iapc_boot_arch = 0xb;
/* fixme */
- fadt->flags = 0x4a5;
+ fadt->flags = 0xa5;
fadt->reset_reg.space_id = 0;
fadt->reset_reg.bit_width = 0;
Index: src/mainboard/asus/m2v-mx_se/amdk8_util.asl
===================================================================
--- src/mainboard/asus/m2v-mx_se/amdk8_util.asl (revision 0)
+++ src/mainboard/asus/m2v-mx_se/amdk8_util.asl (revision 0)
@@ -0,0 +1,315 @@
+/*
+ * Copyright 2005 AMD
+ */
+
+//AMD k8 util for BUSB and res range
+
+ Scope (\_SB)
+ {
+
+ Name (OSTB, Ones)
+ Method (OSTP, 0, NotSerialized)
+ {
+ If (LEqual (^OSTB, Ones))
+ {
+ Store (0x00, ^OSTB)
+ }
+
+ Return (^OSTB)
+ }
+
+ Method (SEQL, 2, Serialized)
+ {
+ Store (SizeOf (Arg0), Local0)
+ Store (SizeOf (Arg1), Local1)
+ If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
+
+ Name (BUF0, Buffer (Local0) {})
+ Store (Arg0, BUF0)
+ Name (BUF1, Buffer (Local0) {})
+ Store (Arg1, BUF1)
+ Store (Zero, Local2)
+ While (LLess (Local2, Local0))
+ {
+ Store (DerefOf (Index (BUF0, Local2)), Local3)
+ Store (DerefOf (Index (BUF1, Local2)), Local4)
+ If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
+
+ Increment (Local2)
+ }
+
+ Return (One)
+ }
+
+
+ Method (DADD, 2, NotSerialized)
+ {
+ Store( Arg1, Local0)
+ Store( Arg0, Local1)
+ Add( ShiftLeft(Local1,16), Local0, Local0)
+ Return (Local0)
+ }
+
+
+ Method (GHCE, 1, NotSerialized) // check if the HC enabled
+ {
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+
+ Method (GHCN, 1, NotSerialized) // get the node num for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
+ Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
+ Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
+ Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+ Return (Local0)
+ }
+
+ Method (GBUS, 2, NotSerialized)
+ {
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (0x00)
+ }
+
+ Method (GWBN, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0000, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0000,,,)
+ })
+ CreateWordField (BUF0, 0x08, BMIN)
+ CreateWordField (BUF0, 0x0A, BMAX)
+ CreateWordField (BUF0, 0x0E, BLEN)
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
+ Store (ShiftRight (Local1, 0x18), BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Increment (BLEN)
+ Return (RTAG (BUF0))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (RTAG (BUF0))
+ }
+
+ Method (GMEM, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, MMIN)
+ CreateDWordField (BUF0, 0x0E, MMAX)
+ CreateDWordField (BUF0, 0x16, MLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x10))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, And (Local2, 0x07)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
+ Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
+ Or (MMAX, 0xFFFF, MMAX)
+ Subtract (MMAX, MMIN, MLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (\_SB.PCI0.TOM1, MMIN)
+ Subtract (MMAX, MMIN, MLEN)
+ Increment (MLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4))
+ {
+ Store (BUF0, Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (GIOR, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, PMIN)
+ CreateDWordField (BUF0, 0x0E, PMAX)
+ CreateDWordField (BUF0, 0x16, PLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x08))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, And (Local2, 0x07)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ Store (And (Local1, 0x01FFF000), PMIN)
+ Store (And (Local2, 0x01FFF000), PMAX)
+ Or (PMAX, 0x0FFF, PMAX)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LGreater (PMAX, PMIN))
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (0x0D00, PMIN)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ Increment (Local4)
+ }
+
+ If (And (Local1, 0x10))
+ {
+ Store (0x03B0, PMIN)
+ Store (0x03DF, PMAX)
+ Store (0x30, PLEN)
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+ }
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4))
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (RTAG, 1, NotSerialized)
+ {
+ Store (Arg0, Local0)
+ Store (SizeOf (Local0), Local1)
+ Subtract (Local1, 0x02, Local1)
+ Multiply (Local1, 0x08, Local1)
+ CreateField (Local0, 0x00, Local1, RETB)
+ Store (RETB, Local2)
+ Return (Local2)
+ }
+ }
+
Index: src/mainboard/asus/m2v-mx_se/Config.lb
===================================================================
--- src/mainboard/asus/m2v-mx_se/Config.lb (revision 3805)
+++ src/mainboard/asus/m2v-mx_se/Config.lb (working copy)
@@ -34,9 +34,16 @@
default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
##WARNING enable caching of whole ROM during CAR
-default XIP_ROM_SIZE = ROM_SIZE
+#default XIP_ROM_SIZE = ROM_SIZE
+#default XIP_ROM_BASE = 0xffffffff + 1 - XIP_ROM_SIZE
+
+##WARNING enable caching of whole ROM during CAR
+##MEGA HACK
+default XIP_ROM_SIZE = 0x80000
default XIP_ROM_BASE = 0xffffffff + 1 - XIP_ROM_SIZE
+
+
arch i386 end
driver mainboard.o
Index: src/mainboard/asus/m2v-mx_se/acpi_tables.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/acpi_tables.c (revision 3805)
+++ src/mainboard/asus/m2v-mx_se/acpi_tables.c (working copy)
@@ -6,7 +6,7 @@
*
* Copyright (C) 2004 Stefan Reinauer <[EMAIL PROTECTED]>
* Copyright (C) 2005 Nick Barker <[EMAIL PROTECTED]>
- * Copyright (C) 2007 Rudolf Marek <[EMAIL PROTECTED]>
+ * Copyright (C) 2007, 2008 Rudolf Marek <[EMAIL PROTECTED]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
@@ -31,7 +31,11 @@
#include <../../../southbridge/via/vt8237r/vt8237r.h>
#include <../../../southbridge/via/k8t890/k8t890.h>
+#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1)
+#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))
+
extern unsigned char AmlCode[];
+extern unsigned char AmlCode_ssdt[];
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -91,6 +95,8 @@
acpi_madt_t *madt;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
+ acpi_slit_t *slit;
+ acpi_header_t *ssdt;
acpi_header_t *dsdt;
/* Align ACPI tables to 16 byte. */
@@ -113,6 +119,10 @@
/* We explicitly add these tables later on: */
printk_debug("ACPI: * FACS\n");
+
+ /* we should align FACS to 64B as per ACPI specs */
+
+ current = ALIGN(current, 64);
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
@@ -158,6 +168,24 @@
current += srat->header.length;
acpi_add_table(rsdt, srat);
+ /* SLIT */
+ printk_debug("ACPI: * SLIT\n");
+ slit = (acpi_slit_t *) current;
+ acpi_create_slit(slit);
+ current+=slit->header.length;
+ acpi_add_table(rsdt,slit);
+
+ /* SSDT */
+ printk_debug("ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ current += ((acpi_header_t *)AmlCode_ssdt)->length;
+ memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
+ update_ssdt((void*)ssdt);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+ acpi_add_table(rsdt,ssdt);
+
printk_info("ACPI: done.\n");
return current;
}
Index: src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- src/mainboard/asus/m2v-mx_se/Options.lb (revision 3805)
+++ src/mainboard/asus/m2v-mx_se/Options.lb (working copy)
@@ -44,7 +44,7 @@
uses STACK_SIZE
uses HEAP_SIZE
# uses USE_OPTION_TABLE
-# uses CONFIG_LB_MEM_TOPK
+uses CONFIG_LB_MEM_TOPK
uses HAVE_ACPI_TABLES
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
@@ -91,7 +91,7 @@
uses SB_HT_CHAIN_ON_BUS0
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_USE_PRINTK_IN_CAR
default ROM_SIZE = 512 * 1024
default FALLBACK_SIZE = 256 * 1024
@@ -152,8 +152,8 @@
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 256 * 1024
# More 1M for pgtbl.
-# default CONFIG_LB_MEM_TOPK = 2048
-default _RAMBASE = 0x00004000
+default CONFIG_LB_MEM_TOPK = 2048
+default _RAMBASE = 0x100000
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default CONFIG_ROM_PAYLOAD = 1
default CC = "$(CROSS_COMPILE)gcc -m32"
Index: src/mainboard/asus/m2v-mx_se/dsdt.asl
===================================================================
--- src/mainboard/asus/m2v-mx_se/dsdt.asl (revision 3805)
+++ src/mainboard/asus/m2v-mx_se/dsdt.asl (working copy)
@@ -22,6 +22,9 @@
DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
{
+ Include ("amdk8_util.asl")
+
+
/* Define the main processor.*/
Scope (\_PR)
{
@@ -47,9 +50,94 @@
Name (_ADR, 0x00)
Name (_UID, 0x00)
Name (_BBN, 0x00)
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0cf7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0xcf8) //,,,, TypeStatic) //00h-cf7h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0d00, // Address Range Minimum
+ 0x0fff, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x300) //,,,, TypeStatic) //00h-cf7h
+ })
+
+
+ Name (BUF1, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x00FF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0100, // Address Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Address Range Minimum
+ 0x0CF8, // Address Range Maximum
+ 0x01, // Address Alignment
+ 0x08, // Address Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0CF8, // Address Length
+ ,, , TypeStatic)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0D00, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0xF300, // Address Length
+ ,, , TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000A0000, // Address Range Minimum
+ 0x000BFFFF, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00020000, // Address Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinNotFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0xC0000000, // Address Range Minimum
+ 0xF12FFFFF, // Address Range Maximum
+ 0x0000000, // Address Translation Offset
+ 0x31300000, // Address Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+
+
+
+// Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+// Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+// Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+
+
+ Return (BUF1)
+ }
+
/* PCI Routing Table */
- /* aaa */
Name (_PRT, Package () {
Package (0x04) { 0x000F0000, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
Index: src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c (revision 3805)
+++ src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c (working copy)
@@ -298,7 +298,6 @@
enable_fid_change();
print_debug("after enable_fid_change\r\n");
- /* FIXME does not work yet */
init_fidvid_bsp(bsp_apicid);
/* Stop the APs so we can start them later in init. */
Index: src/arch/i386/boot/tables.c
===================================================================
--- src/arch/i386/boot/tables.c (revision 3805)
+++ src/arch/i386/boot/tables.c (working copy)
@@ -43,8 +43,8 @@
unsigned long low_table_start, low_table_end, new_low_table_end;
unsigned long rom_table_start, rom_table_end;
- rom_table_start = 0xf0000;
- rom_table_end = 0xf0000;
+ rom_table_start = ((512-64)*1024*1024) - 64*1024;
+ rom_table_end = rom_table_start;
/* Start low addr at 16 bytes instead of 0 because of a buglet
* in the generic linux unzip code, as it tests for the a20 line.
*/
@@ -68,9 +68,10 @@
post_code(0x96);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
- new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point
+ rom_table_end = write_smp_table(rom_table_end);
+ rom_table_end = (rom_table_end+1023) & ~1023;
-#if HAVE_MP_TABLE==1
+#if 0 // HAVE_MP_TABLE==1
/* Don't write anything in the traditional x86 BIOS data segment,
* for example the linux kernel smp need to use 0x467 to pass reset vector
* or use 0x40e/0x413 for EBDA finding...
Index: src/arch/i386/include/arch/acpi.h
===================================================================
--- src/arch/i386/include/arch/acpi.h (revision 3805)
+++ src/arch/i386/include/arch/acpi.h (working copy)
@@ -285,7 +285,7 @@
u32 x_firmware_waking_vector_l;
u32 x_firmware_waking_vector_h;
u8 version;
- u8 resv[33];
+ u8 resv[31];
} __attribute__ ((packed)) acpi_facs_t;
/* These are implemented by the target port */
Index: targets/asus/m2v-mx_se/Config.lb
===================================================================
--- targets/asus/m2v-mx_se/Config.lb (revision 3805)
+++ targets/asus/m2v-mx_se/Config.lb (working copy)
@@ -21,7 +21,7 @@
mainboard asus/m2v-mx_se
romimage "normal"
- option ROM_SIZE = 512 * 1024
+ option ROM_SIZE = (512 * 1024) - 39424
option USE_FALLBACK_IMAGE = 0
option ROM_IMAGE_SIZE = 128 * 1024
option COREBOOT_EXTRA_VERSION=".0Normal"
--
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