On 10.12.2008 11:00, Corey Osgood wrote: > On Tue, Dec 9, 2008 at 12:15 PM, Corey Osgood <[EMAIL PROTECTED]>wrote: > > >> Attached is the net result of what I've done to try to figure out what's >> going on with the cn700, right now it reboots part of the way through >> initram, probably as a result of the GP3 timer not getting reset like it >> should. I'm heading into finals week, so I probably won't be able to get >> back to this until late December. >> >> -Corey >> >> > > Ignore that patch, something Carl-Daniel quoted that I just read reminded me > what the problem was, it was my 1Mbit flash chip not being set up properly. > Attached patch fixes that, checks for CAR area and ROM collision (for C7 at > least), and....well, just look at the patch. > > This patch: > > * Moves non-DRAM early init code out of initram and into stage1, where it > should have been in the first place > * Fixes an issue with GP3 timer causing system reboot (possibly not present > in current svn, but was present in my local copy) > * Fixes serial garbage from stage1 on jetway j7f2 > * Fixes ROM mapping for flash > 512k on vt8237 > * Checks that the CAR base + size allows for the selected ROM size >
Could you move the CAR base + size checks into a separate patch? That would be great. > * Makes a couple minor whitespace changes > * Moves some function prototypes to the headers where they belong > * Nukes some phase2 hackery that belongs in phase4 (eventually) > * Comments out early_mtrr_init() for via/epia-cn, this breaks booting on > jetway j7f2 > early_mtrr_init is broken for ALL chipsets and processors because it disables CAR. I plan to nuke it or at least rewrite it completely. Don't just comment the call out, remove the call altogether. > * Moves troublesome SATA init code into stage1 - change of device class hangs > coreboot > * Gets to vt8237 IDE phase6 init and dies on jetway/j7f2: > Phase 6: Initializing devices... > > Phase 6: Root Device init. > > Phase 6: PCI: 00:10.1 init. > > Primary IDE interface enabled > > Secondary IDE interface enabled > <hang> > > Signed-off-by: Corey Osgood <[EMAIL PROTECTED]> > Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> One question remains, though. You removed some code which I didn't see reappear anywhere. Example follows. > Index: northbridge/via/cn700/initram.c > =================================================================== > --- northbridge/via/cn700/initram.c (revision 1066) > +++ northbridge/via/cn700/initram.c (working copy) > @@ -353,10 +262,6 @@ > pci_conf1_write_config8(dev->d0f3, 0x74, 0x04); > pci_conf1_write_config8(dev->d0f3, 0x75, 0x04); > pci_conf1_write_config8(dev->d0f3, 0x76, 0x00); > - > - /* Thanks to Urbez Santana Roma for this */ > - pci_conf1_write_config8(dev->d1f0, 0x19, 0x1); > - pci_conf1_write_config8(dev->d1f0, 0x1a, 0x1); > } > > /** Is that code obsolete? I couldn't find any mentioning of it in your commit message. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
