Author: myles
Date: 2008-12-10 20:07:16 +0100 (Wed, 10 Dec 2008)
New Revision: 1069
Modified:
coreboot-v3/device/pci_device.c
coreboot-v3/include/device/pci.h
coreboot-v3/northbridge/intel/i945/northbridge.c
coreboot-v3/southbridge/amd/amd8111/ac97.c
coreboot-v3/southbridge/amd/amd8111/acpi.c
coreboot-v3/southbridge/amd/amd8111/ide.c
coreboot-v3/southbridge/amd/amd8111/lpc.c
coreboot-v3/southbridge/amd/amd8111/nic.c
coreboot-v3/southbridge/amd/amd8111/smbus.c
coreboot-v3/southbridge/amd/amd8111/usb.c
coreboot-v3/southbridge/intel/i82801gx/lpc.c
coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
Log:
This patch changes unsigned [int] to u16 for subsystem IDs. They're in the
hardware and have a specific size.
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3/device/pci_device.c 2008-12-10 18:50:54 UTC (rev 1068)
+++ coreboot-v3/device/pci_device.c 2008-12-10 19:07:16 UTC (rev 1069)
@@ -710,8 +710,7 @@
delay(1);
}
-void pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
+void pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/include/device/pci.h
===================================================================
--- coreboot-v3/include/device/pci.h 2008-12-10 18:50:54 UTC (rev 1068)
+++ coreboot-v3/include/device/pci.h 2008-12-10 19:07:16 UTC (rev 1069)
@@ -44,7 +44,7 @@
/* Common pci operations without a standard interface */
struct pci_operations {
/* set the Subsystem IDs for the PCI device */
- void (*set_subsystem)(struct device * dev, unsigned vendor, unsigned
device);
+ void (*set_subsystem)(struct device * dev, u16 vendor, u16 device);
};
/* Common pci bus operations */
@@ -60,8 +60,8 @@
struct pci_driver {
struct device_operations *ops;
- unsigned short vendor;
- unsigned short device;
+ u16 vendor;
+ u16 device;
};
#define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver")))
@@ -94,7 +94,7 @@
unsigned pci_find_next_capability(struct device * dev, unsigned cap, unsigned
last);
unsigned pci_find_capability(struct device * dev, unsigned cap);
struct resource *pci_get_resource(struct device *dev, unsigned long index);
-void pci_dev_set_subsystem(struct device * dev, unsigned vendor, unsigned
device);
+void pci_dev_set_subsystem(struct device * dev, u16 vendor, u16 device);
void pci_domain_read_resources(struct device *dev);
void ram_resource(struct device *dev, unsigned long index,
Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-10 18:50:54 UTC
(rev 1068)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-10 19:07:16 UTC
(rev 1069)
@@ -231,7 +231,7 @@
pci_set_resources(dev);
}
-static void i945_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void i945_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/ac97.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/ac97.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -28,7 +28,7 @@
#include <config.h>
#include "amd8111.h"
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/acpi.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/acpi.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -208,7 +208,7 @@
}
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, 0x7c,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/ide.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/ide.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/ide.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -63,7 +63,7 @@
pci_write_config16(dev, 0x42, word);
}
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/lpc.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/lpc.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -197,7 +197,7 @@
enable_childrens_resources(dev);
}
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/nic.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/nic.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/nic.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -83,7 +83,7 @@
printk(BIOS_DEBUG, "Done\n");
}
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, 0xc8,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/smbus.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/smbus.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -34,7 +34,7 @@
#include <io.h>
#include "amd8111.h"
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, 0x44,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/amd/amd8111/usb.c
===================================================================
--- coreboot-v3/southbridge/amd/amd8111/usb.c 2008-12-10 18:50:54 UTC (rev
1068)
+++ coreboot-v3/southbridge/amd/amd8111/usb.c 2008-12-10 19:07:16 UTC (rev
1069)
@@ -34,7 +34,7 @@
#include "amd8111.h"
-static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void lpci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
pci_write_config32(dev, 0x70,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/intel/i82801gx/lpc.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-12-10 18:50:54 UTC
(rev 1068)
+++ coreboot-v3/southbridge/intel/i82801gx/lpc.c 2008-12-10 19:07:16 UTC
(rev 1069)
@@ -325,7 +325,7 @@
enable_childrens_resources(dev);
}
-static void set_subsystem(struct device * dev, unsigned vendor, unsigned
device)
+static void set_subsystem(struct device * dev, u16 vendor, u16 device)
{
printk(BIOS_DEBUG, "Setting LPC bridge subsystem ID\n");
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
Modified: coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c
===================================================================
--- coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-12-10 18:50:54 UTC
(rev 1068)
+++ coreboot-v3/southbridge/intel/i82801gx/usb_ehci.c 2008-12-10 19:07:16 UTC
(rev 1069)
@@ -49,8 +49,7 @@
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(struct device * dev, unsigned vendor,
- unsigned device)
+static void usb_ehci_set_subsystem(struct device * dev, u16 vendor, u16 device)
{
u8 access_cntl;
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-12-10 18:50:54 UTC
(rev 1068)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-12-10 19:07:16 UTC
(rev 1069)
@@ -248,8 +248,7 @@
}
-void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device)
+void mcp55_pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device)
{
pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-12-10 18:50:54 UTC
(rev 1068)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-12-10 19:07:16 UTC
(rev 1069)
@@ -24,8 +24,7 @@
#define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40
-void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
- unsigned int device);
+void mcp55_pci_dev_set_subsystem(struct device *dev, u16 vendor, u16 device);
extern struct pci_operations mcp55_pci_dev_ops_pci;
#endif /* MCP55_H */
--
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