Index: southbridge/via/vt8237/lpc.c =================================================================== --- southbridge/via/vt8237/lpc.c (revision 1071) +++ southbridge/via/vt8237/lpc.c (working copy) @@ -448,11 +448,13 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_LPC}}}, .constructor = default_device_constructor, + .phase3_chip_setup_dev = vt8237r_init, .phase3_scan = scan_static_bus, .phase4_read_resources = vt8237_read_resources, .phase4_set_resources = pci_set_resources, .phase5_enable_resources = vt8237_enable_resources, - .phase6_init = vt8237r_init, + .phase6_init = NULL, + .ops_pci = &pci_dev_ops_pci, }; struct device_operations vt8237s_lpc = { Index: southbridge/via/vt8237/ide.c =================================================================== --- southbridge/via/vt8237/ide.c (revision 1071) +++ southbridge/via/vt8237/ide.c (working copy) @@ -42,8 +42,11 @@ printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary", sb->ide1_enable ? "enabled" : "disabled"); enables = pci_read_config8(dev, IDE_CS) & ~0x3; + printk(BIOS_DEBUG, "POI1"); enables |= (sb->ide0_enable << 1) | sb->ide1_enable; + printk(BIOS_DEBUG, "POI2"); pci_write_config8(dev, IDE_CS, enables); + printk(BIOS_DEBUG, "POI3"); enables = pci_read_config8(dev, IDE_CS); printk(BIOS_DEBUG, "Enables in reg 0x40 read back as 0x%x\n", enables); @@ -95,11 +98,11 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237_PATA}}}, .constructor = default_device_constructor, - //.phase2_fixup = vt8237_enable, + .phase3_chip_setup_dev = ide_init, //.phase3_scan = 0, - //.phase4_enable_disable = vt8237_enable, - //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_set_resources, - //.phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = ide_init, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + //.phase6_init = ide_init, + .ops_pci = &pci_dev_ops_pci, }; Index: southbridge/via/vt8237/sata.c =================================================================== --- southbridge/via/vt8237/sata.c (revision 1071) +++ southbridge/via/vt8237/sata.c (working copy) @@ -23,10 +23,15 @@ #include "vt8237.h" /* TODO: use phase2_fixup to disable SATA */ +void dummy_sata_init(struct device *dev) +{ + printk(BIOS_DEBUG, "Leaving SATA phase6 init"); +} + /* Causes coreboot to hang, so moved to stage1 code TODO: Fix vt8237s */ -static void sata_i_init(struct device *dev) +void sata_i_init(struct device *dev) { u8 reg; @@ -103,12 +108,13 @@ {.pci = {.vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237R_SATA}}}, .constructor = default_device_constructor, - //.phase3_scan = 0, - //.phase4_enable_disable = vt8237_enable, - //.phase4_read_resources = pci_dev_read_resources, - //.phase4_set_resources = pci_set_resources, - //.phase5_enable_resources = pci_dev_enable_resources, - //.phase6_init = sata_i_init, +// .phase3_chip_setup_dev = sata_i_init, + .phase3_scan = 0, + .phase4_read_resources = pci_dev_read_resources, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_dev_enable_resources, + .phase6_init = dummy_sata_init, + .ops_pci = &pci_dev_ops_pci, }; struct device_operations vt8237s_sata = { Index: northbridge/via/cn700/memctrl.c =================================================================== --- northbridge/via/cn700/memctrl.c (revision 1071) +++ northbridge/via/cn700/memctrl.c (working copy) @@ -33,7 +33,7 @@ u8 ranks, pagec, paged, pagee, pagef, shadowreg; /* Set up the VGA framebuffer size. */ - reg16 = (log2(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15); + reg16 = (log2f(CONFIG_CN700_VIDEO_MB_32) << 12) | (1 << 15); pci_write_config16(dev, 0xa0, reg16); /* Set up VGA timers. */ @@ -57,6 +57,7 @@ /* TODO: This doesn't belong here. At the very least make it a dts * option */ +#if 0 /* Handled in stage1 */ /* Shadow RAM */ pagec = 0xff, paged = 0xff, pagee = 0xff, pagef = 0x30; /* PAGE C, D, E are all read write enable */ @@ -68,22 +69,27 @@ shadowreg |= pagef; pci_write_config8(dev, 0x83, shadowreg); /* vlink mirror */ - vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_CN700_VLINK, 0); - if (vlink_dev) { - pci_write_config8(vlink_dev, 0x61, pagec); - pci_write_config8(vlink_dev, 0x62, paged); - pci_write_config8(vlink_dev, 0x64, pagee); - - shadowreg = pci_read_config8(vlink_dev, 0x63); - shadowreg |= pagef; - pci_write_config8(vlink_dev, 0x63, shadowreg); - } + vlink_dev = dev_find_slot(0, PCI_BDF(0, 7, 0)) + pci_write_config8(vlink_dev, 0x61, pagec); + pci_write_config8(vlink_dev, 0x62, paged); + pci_write_config8(vlink_dev, 0x64, pagee); + shadowreg = pci_read_config8(vlink_dev, 0x63); + shadowreg |= pagef; + pci_write_config8(vlink_dev, 0x63, shadowreg); +#endif } static const struct device_operations memctrl_operations = { - .read_resources = cn700_noop, - .init = memctrl_init, + .id = {.type = DEVICE_ID_PCI, + {.pci = {.vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL}}}, + .constructor = default_device_constructor, + .phase3_scan = scan_static_bus, + .phase4_read_resources = 0, + .phase4_set_resources = pci_set_resources, + .phase5_enable_resources = pci_bus_enable_resources, + .phase6_init = memctrl_init, + .ops_pci = &pci_dev_ops_pci, }; static const struct pci_driver memctrl_driver __pci_driver = { Index: northbridge/via/cn700/stage2.c =================================================================== --- northbridge/via/cn700/stage2.c (revision 1071) +++ northbridge/via/cn700/stage2.c (working copy) @@ -63,10 +63,12 @@ static const u8 ramregs[4] = {0x43, 0x42, 0x41, 0x40}; -static void pci_domain_set_resources(struct device *dev) +static void cn700_pci_domain_set_resources(struct device *dev) { struct device *mc_dev; - u32 pci_tolm; + u32 pci_tolm, tomk, tolmk; + u8 rambits; + int i, idx; printk(BIOS_SPEW, "Entering cn700 pci_domain_set_resources.\n"); @@ -74,37 +76,31 @@ mc_dev = dev_find_pci_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN700_MEMCTRL, 0); - if (mc_dev) { - u32 tomk, tolmk; - u8 rambits; - int i, idx; - - /* - * Once the register value is not zero, the RAM size is - * this register's value multiply 64 * 1024 * 1024. - */ - for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - rambits = pci_read_config8(mc_dev, ramregs[i]); - if (rambits != 0) - break; - } - - tomk = rambits * 64 * 1024; - printk(BIOS_SPEW, "tomk is 0x%x\n", tomk); - /* Compute the Top Of Low Memory (TOLM), in Kb. */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ - tolmk = tomk; - } - /* Report the memory regions. */ - idx = 10; - /* TODO: Hole needed? */ - ram_resource(dev, idx++, 0, 640); /* First 640k */ - /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ - ram_resource(dev, idx++, 768, - (tolmk - 768 - CONFIG_CN700_VIDEO_MB_32 * 1024)); + /* + * Once the register value is not zero, the RAM size is + * this register's value multiply 64 * 1024 * 1024. + */ + for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { + rambits = pci_read_config8(mc_dev, ramregs[i]); + if (rambits != 0) + break; } + tomk = rambits * 64 * 1024; + printk(BIOS_SPEW, "tomk is 0x%x\n", tomk); + /* Compute the Top Of Low Memory (TOLM), in Kb. */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does does not overlap the memory. */ + tolmk = tomk; + } + /* Report the memory regions. */ + idx = 10; + /* TODO: Hole needed? */ + ram_resource(dev, idx++, 0, 640); /* First 640k */ + /* Leave a hole for VGA, 0xa0000 - 0xc0000 */ + ram_resource(dev, idx++, 768, + (tolmk - 768 - CONFIG_CN700_VIDEO_MB_32 * 1024)); + } phase4_assign_resources(&dev->link[0]); } @@ -127,7 +123,7 @@ .constructor = default_device_constructor, .phase3_scan = pci_domain_scan_bus, .phase4_read_resources = pci_domain_read_resources, - .phase4_set_resources = pci_domain_set_resources, + .phase4_set_resources = cn700_pci_domain_set_resources, .phase5_enable_resources = enable_childrens_resources, .phase6_init = 0, }; Index: northbridge/via/cn700/Makefile =================================================================== --- northbridge/via/cn700/Makefile (revision 1071) +++ northbridge/via/cn700/Makefile (working copy) @@ -22,6 +22,7 @@ STAGE2_CHIPSET_SRC += $(src)/northbridge/via/cn700/stage2.c \ $(src)/northbridge/via/cn700/agp.c \ + $(src)/northbridge/via/cn700/memctrl.c \ $(src)/northbridge/via/cn700/pci.c \ $(src)/northbridge/via/cn700/vga.c