On Wed, Dec 17, 2008 at 2:19 PM, Corey Osgood <[email protected]>wrote:
> On Wed, Dec 17, 2008 at 3:24 PM, Corey Osgood <[email protected]>wrote:
>
>> On Wed, Dec 17, 2008 at 2:03 PM, Myles Watson <[email protected]> wrote:
>>
>> Ok, adding it there work. But why does it work there but nowhere else?
>>
> I think it has to do with build order and stage0 vs. stage 2.
self-acked and committed, feel free to move c7.c anywhere you think it
> belongs ;) I've self-acked for expediency, I'm about to brave a snowstorm to
> get to school for a final, and won't be back for probably 4 hours or so. I
> also updated the epia-cn dts, so it should be in the same state as the j7f2
> if you fix the superio stuff.
>
Here's a patch for the dts. (Corey - sorry I forgot to send it to the
list.)
It needs the dtc-links.diff patch from this mail. Or you can just leave the
SuperIO as a child of the domain.
http://www.coreboot.org/pipermail/coreboot/2008-December/043327.html
Thanks,
Myles
Index: coreboot-v3/mainboard/jetway/j7f2/dts
===================================================================
--- coreboot-v3.orig/mainboard/jetway/j7f2/dts
+++ coreboot-v3/mainboard/jetway/j7f2/dts
@@ -43,8 +43,8 @@
/{
mainboard_vendor = "Jetway";
mainboard_name = "J7F2";
- mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */
- mainboard_pci_subsystem_device = "0xbeef"; /* TODO */
+ subsystem_vendor = "0xdead"; /* TODO */
+ subsystem_device = "0xbeef"; /* TODO */
cpus {
/config/("arch/x86/via/c7.dts");
};
@@ -66,23 +66,46 @@
/* How do I represent the bus and pci devices hanging here? */
p...@1,0 {
/config/("northbridge/via/cn700/pci.dts");
- p...@0,1 {
+ p...@0,0 {
/config/("northbridge/via/cn700/vga.dts");
};
};
- p...@f,0 {};
- p...@10,0 {
+ p...@8,0 { /* RaLink RT2561/RT61 802.11g PCI */
+ };
+ p...@a,0 { /* IEEE 1394 Host Controller */
+ };
+ p...@f,0 {
/config/("southbridge/via/vt8237/sata.dts");
};
- p...@10,1 {
+ p...@f,1 {
/config/("southbridge/via/vt8237/ide.dts");
};
+ p...@10,0 {
+ /* /config/("southbridge/via/vt8237/uhci.dts"); */
+ };
+ p...@10,1 {
+ /* /config/("southbridge/via/vt8237/uhci.dts"); */
+ };
+ p...@10,2 {
+ /* /config/("southbridge/via/vt8237/uhci.dts"); */
+ };
+ p...@10,3 {
+ /* /config/("southbridge/via/vt8237/uhci.dts"); */
+ };
+ p...@10,4 {
+ /* /config/("southbridge/via/vt8237/usb2.dts"); */
+ };
p...@11,0 {
/config/("southbridge/via/vt8237/lpc.dts");
+ iop...@4e {
+ /config/("superio/fintek/f71805f/dts");
+ com2enable = "1";
+ };
+ };
+ p...@11,5 { /* Audio */
+ /* /config/("southbridge/via/vt8237/ac97audio.dts"); */
};
- iop...@4e {
- /config/("superio/fintek/f71805f/dts");
- com2enable = "1";
+ p...@12,5 { /* Rhine */
};
};
};
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
