--- coreboot-v2-org/src/northbridge/amd/amdk8/reset_test.c	2008-10-02 19:20:22.000000000 +0800
+++ ../coreboot-v2/src/northbridge/amd/amdk8/reset_test.c	2008-12-19 15:17:38.000000000 +0800
@@ -1,5 +1,7 @@
 #include <stdint.h>
 #include <cpu/x86/lapic.h>
+#include <arch/romcc_io.h>
+
 #define NODE_ID		0x60
 #define	HT_INIT_CONTROL 0x6c
 
--- coreboot-v2-org/src/southbridge/amd/sb600/sb600_reset.c	2008-12-01 19:37:20.000000000 +0800
+++ ../coreboot-v2/src/southbridge/amd/sb600/sb600_reset.c	2008-12-19 15:59:55.000000000 +0800
@@ -24,8 +24,6 @@
 	(((DEV) & 0x1F) << 15) | \
 	(((FN)  & 0x7) << 12))
 
-typedef u32 device_t;
-
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
 void hard_reset(void)