Intel 82865P/PE northbridge uses special device #6 (called Overflow Device in datasheet) for keeping the MCH registers. This device is usually hidden by BIOS and can be enabled by setting bit 1 (0x02) in PCI config register 0xF4 in device 00:00.0 (the NB device) and using fake-php to rescan PCI bus.
Signed-off-by: Michał Mirosław <[email protected]> Index: util/inteltool/inteltool.h =================================================================== --- util/inteltool/inteltool.h (wersja 3826) +++ util/inteltool/inteltool.h (kopia robocza) @@ -44,6 +44,7 @@ #define PCI_DEVICE_ID_INTEL_ICH8M 0x2815 #define PCI_DEVICE_ID_INTEL_82845 0x1a30 +#define PCI_DEVICE_ID_INTEL_82865P 0x2570 #define PCI_DEVICE_ID_INTEL_82945P 0x2770 #define PCI_DEVICE_ID_INTEL_82945GM 0x27a0 #define PCI_DEVICE_ID_INTEL_PM965 0x2a00 @@ -61,7 +62,7 @@ unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); -int print_mchbar(struct pci_dev *nb); +int print_mchbar(struct pci_dev *nb, struct pci_dev *d6); int print_pmbase(struct pci_dev *sb); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb); Index: util/inteltool/pcie.c =================================================================== --- util/inteltool/pcie.c (wersja 3826) +++ util/inteltool/pcie.c (kopia robocza) @@ -42,7 +42,7 @@ epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82865P: printf("This northbrigde does not have EPBAR.\n"); return 1; default: @@ -88,7 +88,7 @@ dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe; dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; break; - case 0x1234: // Dummy for non-existent functionality + case PCI_DEVICE_ID_INTEL_82865P: printf("This northbrigde does not have DMIBAR.\n"); return 1; default: @@ -136,8 +136,8 @@ pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; break; - case 0x1234: // Dummy for non-existent functionality - printf("Error: This northbrigde does not have PCIEXBAR.\n"); + case PCI_DEVICE_ID_INTEL_82865P: + printf("This northbrigde does not have PCIEXBAR.\n"); return 1; default: printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n"); Index: util/inteltool/memory.c =================================================================== --- util/inteltool/memory.c (wersja 3826) +++ util/inteltool/memory.c (kopia robocza) @@ -25,7 +25,7 @@ /* * (G)MCH MMIO Config Space */ -int print_mchbar(struct pci_dev *nb) +int print_mchbar(struct pci_dev *nb, struct pci_dev *d6) { int i, size = (16 * 1024); volatile uint8_t *mchbar; @@ -43,6 +43,14 @@ mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; break; + case PCI_DEVICE_ID_INTEL_82865P: + if (!d6) { + printf("Can't dump MCHBAR as this northbrigde's device #6 was hidden by BIOS.\n"); + return 1; + } + mchbar_phys = pci_read_long(d6, 0x10) & 0xfffffffe; + size = 4 * 1024; + break; case 0x1234: // Dummy for non-existent functionality printf("This northbrigde does not have MCHBAR.\n"); return 1; Index: util/inteltool/inteltool.c =================================================================== --- util/inteltool/inteltool.c (wersja 3826) +++ util/inteltool/inteltool.c (kopia robocza) @@ -30,6 +30,7 @@ char *name; } supported_chips_list[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865P, "i865P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" }, @@ -108,7 +110,7 @@ int main(int argc, char *argv[]) { struct pci_access *pacc; - struct pci_dev *sb, *nb; + struct pci_dev *sb, *nb, *d6; int i, opt, option_index = 0; unsigned int id; @@ -227,6 +229,10 @@ exit(1); } + d6 = pci_get_dev(pacc, 0, 0, 0x06, 0); + if (d6) + pci_fill_info(d6, PCI_FILL_IDENT|PCI_FILL_BASES|PCI_FILL_SIZES|PCI_FILL_CLASS); + id = cpuid(1); printf("Intel CPU: Family %x, Model %x\n", (id >> 8) & 0xf, (id >> 4) & 0xf); @@ -263,7 +269,7 @@ } if (dump_mchbar) { - print_mchbar(nb); + print_mchbar(nb, d6); printf("\n\n"); } @@ -288,6 +294,8 @@ } /* Clean up */ + if (d6) + pci_free_dev(d6); pci_free_dev(nb); pci_free_dev(sb); pci_cleanup(pacc); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
