On Wed, Dec 31, 2008 at 12:33 PM, ron minnich <[email protected]> wrote:
> can you send me the full build log? Sure. Thanks, Myles
CP build/config.h GEN build/build.h BUILD DUMMY VPD CC build/lib/uart8250.o CC build/lib/mem.o CC build/lib/lar.o CC build/lib/delay.o CC build/lib/vtxprintf.o CC build/lib/vsprintf.o CC build/lib/console.o CC build/lib/string.o CC build/lib/lzma.o CC build/lib/elfboot.o CC build/arch/x86/stage1.o CC build/arch/x86/serial.o CC build/arch/x86/udelay_io.o CC build/arch/x86/mc146818rtc.o CC build/arch/x86/post_code.o CC build/arch/x86/pci_ops_conf1.o CC build/arch/x86/archelfboot.o CC build/arch/x86/amd/k8/stage1.o CC build/lib/clog2.o CC build/mainboard/tyan/s2892/stage1.o CC build/arch/x86/resourcemap.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/resourcemap.c:66:2: warning: #warning make sure offset_bus is right for extended PCI addressing CC build/arch/x86/amd/model_fxx/dualcore_id.o CC build/arch/x86/amd/model_fxx/stage1.o HOSTCC build/util/dtc/dtc.o HOSTCC build/util/dtc/livetree.o HOSTCC build/util/dtc/flattree.o HOSTCC build/util/dtc/data.o HOSTCC build/util/dtc/treesource.o HOSTCC build/util/dtc/fstree.o BISON build/util/dtc/dtc-parser.tab.c HOSTCC build/util/dtc/dtc-parser.tab.o HOSTCC build/util/dtc/dtc DTC build/statictree.h DTC mainboard/tyan/s2892/dts (dts->lbh) CC build/northbridge/amd/k8/get_nodes.o CC build/northbridge/amd/k8/incoherent_ht_chain.o CC build/northbridge/amd/k8/libstage1.o CC build/southbridge/nvidia/ck804/stage1.o CC build/southbridge/nvidia/ck804/stage1_smbus.o CC build/southbridge/nvidia/ck804/shared_smbus.o CC build/southbridge/nvidia/ck804/stage1_enable_rom.o CC build/arch/x86/stage1_mtrr.o CC build/superio/winbond/w83627hf/stage1.o CC build/device/pnp_raw.o HOSTCC build/util/options/build_opt_tbl.o HOSTCC build/util/options/build_opt_tbl OPTIONS build/mainboard/tyan/s2892/option_table.c CC build/mainboard/tyan/s2892/option_table.o CC build/arch/x86/amd/stage0.o In file included from /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/amd/stage0.S:366: /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/amd/../stage0_common.S:152:2: warning: #warning Everything below this line and two bytes above this line is being clobbered by LAR. For the discussion about this, see the thread at www.coreboot.org/pipermail/coreboot/2008-December/042771.html AS build/arch/x86/amd/stage0.o CHECK stage0 (non-empty writable/allocatable sections) CC build/stage0.init OBJCOPY build/stage0.init OBJCOPY build/stage0.init (prefixing stage0) TEST build/stage0.init Error. Bootblock got too big. NM build/stage0.init BUILD build/coreboot.bootblock BUILD LAR BUILD LZMA BUILD NRV2B HOSTCC build/util/lar/lar.o HOSTCC build/util/lar/stream.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/util/lar/stream.c:838:2: warning: #warning We should check all chunks of free space in the LAR. Right now we do not return the maximum size, but the size of the first chunk. HOSTCC build/util/lar/lib.o HOSTCXX build/util/lzma/LZMAEncoder.o HOSTCXX build/util/lzma/LZInWindow.o HOSTCXX build/util/lzma/RangeCoderBit.o HOSTCXX build/util/lzma/StreamUtils.o HOSTCXX build/util/lzma/OutBuffer.o HOSTCXX build/util/lzma/Alloc.o HOSTCXX build/util/lzma/CRC.o HOSTCC build/util/nrv2b/nrv2b-compress.o HOSTCXX build/util/lar/lar HOSTCXX build/util/lzma/minilzma.o CC build/coreboot.initram (XIP) /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/raminit.c:46:2: warning: #warning where to we define supported DIMM types /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/raminit.c:724:2: warning: #warning "FIXME implement a better test for opterons" /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/amd/model_fxx/fidvid.c:37:2: warning: #warning document these settings! /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/amd/model_fxx/init_cpus.c:344:2: warning: #warning ignore init_detectedx CHECK initram (non-empty writable/allocatable sections) WRAP build/coreboot.initram (PIC->non-PIC) AS initram_picwrapper.s LD build/coreboot.initram NM build/coreboot.initram CC build/lib/stage2.o CC build/lib/tables.o CC build/lib/compute_ip_checksum.o CC build/arch/x86/archtables.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/archtables.c:43:2: warning: #warning enable disabled code in archtables.c /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/arch/x86/archtables.c:140:2: warning: #warning GDT should be placed in a reserved position from the beginning on. CC build/arch/x86/coreboot_table.o CC build/arch/x86/multiboot.o CC build/arch/x86/pci_ops_auto.o CC build/arch/x86/keyboard.o CC build/arch/x86/i8259.o CC build/arch/x86/isa-dma.o CC build/arch/x86/mtrr.o CC build/device/device.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/device/device.c:564:2: warning: #warning Modify allocate_vga_resource so it is less PCI centric. /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/device/device.c:816:2: warning: #warning do we call phase3_enable here. CC build/device/device_util.o CC build/device/root_device.o CC build/device/pci_device.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/device/pci_device.c:1124:2: warning: #warning This check needs checking. CC build/device/pci_ops.o CC build/device/pci_rom.o CC build/device/pnp_device.o CC build/device/smbus_ops.o CC build/device/hypertransport.o CC build/device/pcix_device.o CC build/mainboard/tyan/s2892/mainboard.o CC build/northbridge/amd/k8/get_sblk_pci1234.o CC build/northbridge/amd/k8/common.o CC build/northbridge/amd/k8/cpu.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/cpu.c:133:2: warning: #warning clean this mess up /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/cpu.c:191:2: warning: #warning fill cpuid; right now it is zero /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/cpu.c:51: warning: âcpu_bus_scanâ defined but not used /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/cpu.c:228: warning: âcpu_bus_initâ defined but not used /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/cpu.c:235: warning: âcpu_bus_noopâ defined but not used CC build/northbridge/amd/k8/domain.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/domain.c:253:2: warning: #warning "FIXME handle interleaved nodes" /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/domain.c:259:2: warning: #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole" CC build/northbridge/amd/k8/pci.o CC build/northbridge/amd/k8/mcf3.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/mcf3.c:18:2: warning: #warning Broken hard_reset /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/northbridge/amd/k8/mcf3.c:23:2: warning: #warning Make AGP_APERTURE_SIZE a CONFIG variable CC build/northbridge/amd/k8/apic.o CC build/northbridge/amd/k8/util.o CC build/southbridge/amd/amd8131/amd8131_bridge.o CC build/southbridge/nvidia/ck804/ck804.o CC build/southbridge/nvidia/ck804/ide.o CC build/southbridge/nvidia/ck804/pci.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/southbridge/nvidia/ck804/pci.c:52:2: warning: #warning 64-bit disabled here CC build/southbridge/nvidia/ck804/lpc.o CC build/southbridge/nvidia/ck804/pcie.o CC build/southbridge/nvidia/ck804/sata.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/southbridge/nvidia/ck804/sata.c:34: warning: âsata_com_resetâ defined but not used CC build/southbridge/nvidia/ck804/smbus.o CC build/southbridge/nvidia/ck804/usb.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/southbridge/nvidia/ck804/usb.c: In function âusb1_initâ: /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/southbridge/nvidia/ck804/usb.c:32: warning: unused variable âconfâ CC build/southbridge/nvidia/ck804/usb2.o CC build/superio/winbond/w83627hf/superio.o /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/superio/winbond/w83627hf/superio.c:60:2: warning: #warning Fix CMOS handling /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/superio/winbond/w83627hf/superio.c:112:2: warning: #warning init_uart8250 /home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/superio/winbond/w83627hf/superio.c:118:2: warning: #warning init_uart8250 DTC build/mainboard/tyan/s2892/statictree.c DTC mainboard/tyan/s2892/dts (dts->lb) CC build/mainboard/tyan/s2892/statictree.o CC build/util/x86emu/vm86.o CC build/util/x86emu/vm86_gdt.o AR build/util/x86emu/libx86emu.a LD build/coreboot.stage2 OBJCOPY build/option_table LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. It is the wrong size; it should be 20480 bytes and it is 20560 bytes Error adding the bootblock to the LAR. make: *** [/home/myles/buildrom/buildrom-devel/work/coreboot-v3/svn/build/coreboot.rom] Error 1
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