Author: myles
Date: 2008-12-31 21:02:03 +0100 (Wed, 31 Dec 2008)
New Revision: 1093
Modified:
coreboot-v3/mainboard/kontron/986lcd-m/dts
coreboot-v3/northbridge/intel/i945/northbridge.c
coreboot-v3/northbridge/intel/i945/northbridge.dts
Log:
This patch fixes up kontron for the new resource allocator. More
could be done.
northbridge/intel/i945/northbridge.dts
Remove bridge flag. Northbridges don't have children. The domains
they implement do.
northbridge/intel/i945/northbridge.c
Add IORESOURCE_BRIDGE flags and change the limit for MMIO to avoid ROM.
mainboard/kontron/986lcd-m/dts
Make PCI devices children of the domain and add a few devices.
Signed-off-by: Myles Watson <[email protected]>
Acked-by: Ronald G. Minnich <[email protected]>
Modified: coreboot-v3/mainboard/kontron/986lcd-m/dts
===================================================================
--- coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-12-31 20:00:30 UTC (rev
1092)
+++ coreboot-v3/mainboard/kontron/986lcd-m/dts 2008-12-31 20:02:03 UTC (rev
1093)
@@ -145,55 +145,90 @@
};
dom...@0 {
/config/("northbridge/intel/i945/northbridge.dts");
- /* guesses; we need a real lspci */
- p...@0,0 {
- p...@1b,0 {
-
/config/("southbridge/intel/i82801gx/ac97audio.dts");
- };
- p...@1c,0 {
-
/config/("southbridge/intel/i82801gx/pcie1.dts");
- };
- p...@1c,1 {
-
/config/("southbridge/intel/i82801gx/pcie2.dts");
- };
- p...@1c,2{
-
/config/("southbridge/intel/i82801gx/pcie3.dts");
- };
- p...@1d,0{
-
/config/("southbridge/intel/i82801gx/usb1.dts");
- };
- p...@1d,1{
-
/config/("southbridge/intel/i82801gx/usb2.dts");
- };
- p...@1d,2{
-
/config/("southbridge/intel/i82801gx/usb3.dts");
- };
- p...@1d,3{
-
/config/("southbridge/intel/i82801gx/usb4.dts");
- };
- p...@1d,7{
-
/config/("southbridge/intel/i82801gx/usb_ehci.dts");
- };
- p...@1e,0{
-
/config/("southbridge/intel/i82801gx/pci.dts");
- };
- p...@1f,0{/* which ich? */
-
/config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts");
- };
- p...@1f,1{
-
/config/("southbridge/intel/i82801gx/ide.dts");
- };
- p...@1f,2{
-
/config/("southbridge/intel/i82801gx/sata.dts");
- };
- p...@1f,3{
-
/config/("southbridge/intel/i82801gx/smbus.dts");
- };
-
+ p...@0,0 {
+ /config/("northbridge/intel/i945/mc.dts");
};
- iop...@2e {
- /config/("superio/winbond/w83627thg/dts");
- com1enable = "1";
+ p...@1,0 { /* PCIe */
+ disabled;
};
+ p...@2,0 { /* Onboard VGA. */
+ rom_address = "0xfff00000"; /* Shouldn't this be a lar
path? */
+ };
+ p...@2,1 { /* Display controller. */
+ };
+ p...@1b,0 {
+ /config/("southbridge/intel/i82801gx/ac97audio.dts");
+ };
+ p...@1c,0 {
+ /config/("southbridge/intel/i82801gx/pcie1.dts");
+ };
+ p...@1c,1 {
+ /config/("southbridge/intel/i82801gx/pcie2.dts");
+ };
+ p...@1c,2{
+ /config/("southbridge/intel/i82801gx/pcie3.dts");
+ };
+ p...@1c,3{ disabled; }; /* PCIe port 4 */
+ p...@1c,4{ disabled; }; /* PCIe port 5 */
+ p...@1c,5{ disabled; }; /* PCIe port 6 */
+ p...@1d,0{
+ /config/("southbridge/intel/i82801gx/usb1.dts");
+ };
+ p...@1d,1{
+ /config/("southbridge/intel/i82801gx/usb2.dts");
+ };
+ p...@1d,2{
+ /config/("southbridge/intel/i82801gx/usb3.dts");
+ };
+ p...@1d,3{
+ /config/("southbridge/intel/i82801gx/usb4.dts");
+ };
+ p...@1d,7{
+ /config/("southbridge/intel/i82801gx/usb_ehci.dts");
+ };
+ p...@1e,0{
+ /config/("southbridge/intel/i82801gx/pci.dts");
+ };
+ p...@1e,2{ disabled; }; /* AC'97 Audio */
+ p...@1e,3{ disabled; }; /* AC'97 Modem */
+ p...@1f,0{/* which ich? */
+ /config/("southbridge/intel/i82801gx/ich7m_dh_lpc.dts");
+ iop...@2e {
+ /config/("superio/winbond/w83627thg/dts");
+ com1enable = "1";
+ com2enable = "1";
+ kbenable = "1";
+ /* irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
*/
+ gameenable = "1";
+ gpio2enable = "1";
+ gpio34enable = "1";
+ hwmenable = "1";
+ };
+ iop...@4e {
+ /config/("superio/winbond/w83627thg/dts");
+ com1enable = "1";
+ com1io = "0x3e8";
+ com1irq = "11";
+ com2enable = "1";
+ com2io = "0x2e8";
+ com2irq = "10";
+ };
+ };
+ p...@1f,1{ /* Disabled and commented out in v2. */
+ /config/("southbridge/intel/i82801gx/ide.dts");
+ disabled;
+ };
+ p...@1f,2{
+ /config/("southbridge/intel/i82801gx/sata.dts");
+ };
+ p...@1f,3{
+ /config/("southbridge/intel/i82801gx/smbus.dts");
+ };
+ /* Disabled and commented out in v2.
+ * p...@1f,4{
+ * /config/("southbridge/intel/i82801gx/codec.dts");
+ * disabled;
+ * };
+ */
};
};
Modified: coreboot-v3/northbridge/intel/i945/northbridge.c
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-31 20:00:30 UTC
(rev 1092)
+++ coreboot-v3/northbridge/intel/i945/northbridge.c 2008-12-31 20:02:03 UTC
(rev 1093)
@@ -51,8 +51,8 @@
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
- resource->flags =
- IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_BRIDGE;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
@@ -60,9 +60,10 @@
resource->size = 0;
resource->align = 0;
resource->gran = 0;
- resource->limit = 0xffffffffUL;
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ /* This is a hack. I don't know all the right reserved regions. */
+ resource->limit = 0xfeffffffUL;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_BRIDGE;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
Modified: coreboot-v3/northbridge/intel/i945/northbridge.dts
===================================================================
--- coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-12-31 20:00:30 UTC
(rev 1092)
+++ coreboot-v3/northbridge/intel/i945/northbridge.dts 2008-12-31 20:02:03 UTC
(rev 1093)
@@ -19,4 +19,5 @@
*/
{
device_operations = "i945_pci_domain_ops";
+ bridge;
};
--
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