Patch to add support for Winbond w83627uhg SuperIO.
(This is my first submission. Let me know if I did it wrong.)
Signed-off-by: Dan Lykowski <[email protected]>
---
Index: src/superio/winbond/w83627uhg/w83627uhg_early_serial.c
===================================================================
--- src/superio/winbond/w83627uhg/w83627uhg_early_serial.c (revision 0)
+++ src/superio/winbond/w83627uhg/w83627uhg_early_serial.c (revision 0)
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ * Copyright (C) 2009 Dynon Avionics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include "w83627uhg.h"
+
+static inline void pnp_enter_ext_func_mode(device_t dev)
+{
+ unsigned int port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ unsigned int port = dev >> 8;
+ outb(0xaa, port);
+}
+
+static void w83627uhg_set_input_clk_sel(device_t dev, uint8_t speed_24mhz)
+{
+ /* Set the input clock to 24 or 48 mhz. */
+ uint8_t value;
+ value = pnp_read_config( dev, 0x24 );
+ value &= ~(1<<6);
+ if(!speed_24mhz) {
+ value |= (1<<6);
+ }
+ pnp_write_config( dev, 0x24, value );
+}
+
+static void w83627uhg_enable_serial(device_t dev, unsigned int iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
Index: src/superio/winbond/w83627uhg/Config.lb
===================================================================
--- src/superio/winbond/w83627uhg/Config.lb (revision 0)
+++ src/superio/winbond/w83627uhg/Config.lb (revision 0)
@@ -0,0 +1,2 @@
+config chip.h
+object superio.o
Index: src/superio/winbond/w83627uhg/superio.c
===================================================================
--- src/superio/winbond/w83627uhg/superio.c (revision 0)
+++ src/superio/winbond/w83627uhg/superio.c (revision 0)
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ * Copyright (C) 2009 Dynon Avionics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "w83627uhg.h"
+
+static void w83627uhg_enter_ext_func_mode(device_t dev)
+{
+ outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.u.pnp.port);
+}
+static void w83627uhg_exit_ext_func_mode(device_t dev)
+{
+ outb(0xaa, dev->path.u.pnp.port);
+}
+
+
+static void set_uart_clock_source( device_t dev, uint8_t uart_clock ) {
+ /* Set the uart clock source */
+ /* Warning, the Kernel will need to be adjusted since it assumes a 1.8462MHz clock */
+
+ /* Possible Uart Clock Source Speeds are:
+ 0 = 1.8462MHz (default)
+ 1 = 2MHz
+ 2 = 24MHz
+ 3 = 14.769 MHz
+ The faster clocks allow for baudrates up to 2mbits
+ */
+
+ uint8_t value;
+ w83627uhg_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ value = pnp_read_config( dev, 0xF0 );
+ value &= ~0x03;
+ value |= (uart_clock & 0x03);
+ pnp_write_config( dev, 0xF0, value );
+ w83627uhg_exit_ext_func_mode(dev);
+}
+
+static void w83627uhg_init(device_t dev)
+{
+ struct superio_winbond_w83627uhg_config *conf;
+ struct resource *res0, *res1;
+ /* Wishlist handle well known programming interfaces more
+ * generically.
+ */
+ if (!dev->enabled) {
+ return;
+ }
+ conf = dev->chip_info;
+ switch(dev->path.u.pnp.device) {
+ case W83627UHG_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ /*set_uart_clock_source( dev, 0 );*/
+ init_uart8250(res0->base, &conf->com1);
+ break;
+ case W83627UHG_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ /*set_uart_clock_source( dev, 0 );*/
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ case W83627UHG_SP3:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ /*set_uart_clock_source( dev, 0 );*/
+ init_uart8250(res0->base, &conf->com3);
+ break;
+ case W83627UHG_SP4:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ /*set_uart_clock_source( dev, 0 );*/
+ init_uart8250(res0->base, &conf->com4);
+ break;
+ case W83627UHG_SP5:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ /*set_uart_clock_source( dev, 0 );*/
+ init_uart8250(res0->base, &conf->com5);
+ break;
+ case W83627UHG_SP6:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ /*set_uart_clock_source( dev, 0 );*/
+ init_uart8250(res0->base, &conf->com6);
+ break;
+ case W83627UHG_KBC:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
+ init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+ break;
+ }
+}
+
+static void w83627uhg_set_resources(device_t dev)
+{
+ w83627uhg_enter_ext_func_mode(dev);
+ pnp_set_resources(dev);
+ w83627uhg_exit_ext_func_mode(dev);
+}
+
+static void w83627uhg_enable_resources(device_t dev)
+{
+ w83627uhg_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ w83627uhg_exit_ext_func_mode(dev);
+}
+
+static void w83627uhg_enable(device_t dev)
+{
+ w83627uhg_enter_ext_func_mode(dev);
+ pnp_enable(dev);
+ w83627uhg_exit_ext_func_mode(dev);
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = w83627uhg_set_resources,
+ .enable_resources = w83627uhg_enable_resources,
+ .enable = w83627uhg_enable,
+ .init = w83627uhg_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ // No 4 { 0,},
+ { &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627UHG_GPIO3_4, },
+ { &ops, W83627UHG_WDTO_PLED_GPIO5_6, },
+ { &ops, W83627UHG_GPIO1_2,},
+ { &ops, W83627UHG_ACPI, PNP_IRQ0, },
+ { &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } },
+ { &ops, W83627UHG_PECI_SST,},
+ { &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &ops,
+ sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
+}
+
+struct chip_operations superio_winbond_w83627uhg_ops = {
+ CHIP_NAME("Winbond W83627UHG Super I/O")
+ .enable_dev = enable_dev,
+};
Index: src/superio/winbond/w83627uhg/chip.h
===================================================================
--- src/superio/winbond/w83627uhg/chip.h (revision 0)
+++ src/superio/winbond/w83627uhg/chip.h (revision 0)
@@ -0,0 +1,9 @@
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_winbond_w83627uhg_ops;
+
+struct superio_winbond_w83627uhg_config {
+ struct uart8250 com1, com2, com3, com4, com5, com6;
+ struct pc_keyboard keyboard;
+};
Index: src/superio/winbond/w83627uhg/w83627uhg.h
===================================================================
--- src/superio/winbond/w83627uhg/w83627uhg.h (revision 0)
+++ src/superio/winbond/w83627uhg/w83627uhg.h (revision 0)
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ * Copyright (C) 2009 Dynon Avionics.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $
+ */
+
+#define W83627UHG_FDC 0 /* Floppy */
+#define W83627UHG_PP 1 /* Parallel Port */
+#define W83627UHG_SP1 2 /* Com1 */
+#define W83627UHG_SP2 3 /* Com2 */
+#define W83627UHG_KBC 5 /* Keyboard & Mouse */
+#define W83627UHG_SP3 6 /* Com3 */
+#define W83627UHG_GPIO3_4 7
+#define W83627UHG_WDTO_PLED_GPIO5_6 8
+#define W83627UHG_GPIO1_2 9
+#define W83627UHG_ACPI 10
+#define W83627UHG_HWM 11 /* Hardware Monitor */
+#define W83627UHG_PECI_SST 12
+#define W83627UHG_SP4 13 /* Com 4 */
+#define W83627UHG_SP5 14 /* Com 5 */
+#define W83627UHG_SP6 15 /* Com 6 */
--
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