Author: uwe Date: 2009-01-08 17:14:12 +0100 (Thu, 08 Jan 2009) New Revision: 1107
Modified: coreboot-v3/northbridge/intel/i945/ich7.h coreboot-v3/southbridge/intel/i82801gx/i82801gx.h coreboot-v3/southbridge/intel/i82801gx/lpc.c Log: Port r3747, r3732, r3733 from v2 to v3 (build-tested on v3): src/northbridge/intel/i945/ich7.h: Thanks to Uwe Hermann for spotting this typo. src/southbridge/intel/i82801gx/i82801gx_lpc.c: The enable_hpet() code in intel/i82801gx will not work with the ICH7 southbridge (but it might work with ICH4/ICH5 or so). The ICH7 needs a different init code. Drop the non-working code for now. src/southbridge/intel/i82801gx/i82801gx.h: Drop #defines for registers that are not existant on the ICH7. Also, fix BIOS_CNTL, which is 0xdc on ICH7. Build-tested with kontron/986lcd-m. Signed-off-by: Uwe Hermann <[email protected]> Acked-by: Uwe Hermann <[email protected]> Modified: coreboot-v3/northbridge/intel/i945/ich7.h =================================================================== --- coreboot-v3/northbridge/intel/i945/ich7.h 2009-01-08 16:01:25 UTC (rev 1106) +++ coreboot-v3/northbridge/intel/i945/ich7.h 2009-01-08 16:14:12 UTC (rev 1107) @@ -60,7 +60,7 @@ #define RP2D 0x0130 /* 32bit */ #define RP2BA 0x0138 /* 64bit */ #define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0138 /* 64bit */ +#define RP3BA 0x0148 /* 64bit */ #define RP4D 0x0150 /* 32bit */ #define RP4BA 0x0158 /* 64bit */ #define HDD 0x0160 /* 32bit */ Modified: coreboot-v3/southbridge/intel/i82801gx/i82801gx.h =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/i82801gx.h 2009-01-08 16:01:25 UTC (rev 1106) +++ coreboot-v3/southbridge/intel/i82801gx/i82801gx.h 2009-01-08 16:14:12 UTC (rev 1107) @@ -22,18 +22,20 @@ #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H /* warning: included in stage1 and stage2 */ -#define PCI_DMA_CFG 0x90 #define SERIRQ_CNTL 0x64 -#define GEN_CNTL 0xd0 -#define GEN_STS 0xd4 -#define RTC_CONF 0xd8 + #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +/* GEN_PMCON_3 bits */ +#define RTC_BATTERY_DEAD (1 << 2) +#define RTC_POWER_FAILED (1 << 1) +#define SLEEP_AFTER_POWER_FAIL (1 << 0) + #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define BIOS_CNTL 0x4E +#define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -46,28 +48,10 @@ #define PIRQG_ROUT 0x6A #define PIRQH_ROUT 0x6B -#define FUNC_DIS 0xF2 - #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define SBUS_NUM 0x19 -#define SUB_BUS_NUM 0x1A -#define SMLT 0x1B -#define IOBASE 0x1C -#define IOLIM 0x1D -#define MEMBASE 0x20 -#define MEMLIM 0x22 -#define CNF 0x50 -#define MTT 0x70 -#define PCI_MAST_STS 0x82 - -/* GEN_PMCON_3 bits */ -#define RTC_BATTERY_DEAD (1 << 2) -#define RTC_POWER_FAILED (1 << 1) -#define SLEEP_AFTER_POWER_FAIL (1 << 0) - -/* PCI Configuration Space (D31:F1) */ +/* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ #define IDE_DECODE_ENABLE (1 << 15) @@ -82,7 +66,7 @@ #define PCB1 (1 << 1) #define PCB0 (1 << 0) -/* PCI Configuration Space (D31:F3) */ +/* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 Modified: coreboot-v3/southbridge/intel/i82801gx/lpc.c =================================================================== --- coreboot-v3/southbridge/intel/i82801gx/lpc.c 2009-01-08 16:01:25 UTC (rev 1106) +++ coreboot-v3/southbridge/intel/i82801gx/lpc.c 2009-01-08 16:14:12 UTC (rev 1107) @@ -201,22 +201,7 @@ static void enable_hpet(struct device *dev) { - u32 reg32; - u32 code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk(BIOS_DEBUG, "Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); + /* TODO */ } static void i82801gx_lock_smm(struct device *dev) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
