Author: myles Date: 2009-01-08 17:22:39 +0100 (Thu, 08 Jan 2009) New Revision: 1109
Modified: coreboot-v3/mainboard/amd/dbm690t/dts coreboot-v3/mainboard/amd/serengeti/dts coreboot-v3/mainboard/gigabyte/m57sli/dts coreboot-v3/northbridge/amd/k8/domain.c Log: This is a small HT fixup until HT links get figured out better. It removes processors from the list of devices on the domain's bus so that pci_scan_bus won't disable them, then scans for them, then puts them back. There are lots of other ways to do this, but this one seemed minimally invasive and ends up with a correct tree. The dts fixups I should have put in with the other K8 patch for the new resource allocator. I went to the v2 Config.lb files and tried to get them as complete as possible. Signed-off-by: Myles Watson <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: coreboot-v3/mainboard/amd/dbm690t/dts =================================================================== --- coreboot-v3/mainboard/amd/dbm690t/dts 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/mainboard/amd/dbm690t/dts 2009-01-08 16:22:39 UTC (rev 1109) @@ -66,52 +66,75 @@ /{ device_operations="dbm690t"; mainboard_vendor = "AMD"; - mainboard_name = "Serengeti"; + mainboard_name = "dbm690t"; cpus { }; a...@0 { }; dom...@0 { /config/("northbridge/amd/k8/domain"); - p...@1,0{ + /* Make sure that the HT device is first; if it isn't found, + * the rest of the devices won't be found. + */ + p...@0 { + /config/("southbridge/amd/rs690/ht.dts"); }; - /* guesses; we need a real lspci */ - p...@18,0 { - /config/("northbridge/amd/k8/pci"); - /* make sure that the ht device is first, as it controls many other things. */ - pci0 { - /config/("southbridge/amd/rs690/ht.dts"); - }; - pci1{ + p...@1{ + /config/("southbridge/amd/sb600/pci.dts"); + p...@5{ /config/("southbridge/amd/rs690/gfx.dts"); }; - pci2{ - /config/("southbridge/amd/rs690/pcie.dts"); + }; + p...@6{ /* Port 2 */ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + p...@7{ /* Port 3 */ + /config/("southbridge/amd/rs690/pcie.dts"); + }; + p...@12{ + /config/("southbridge/amd/sb600/hda.dts"); + }; + p...@13,0{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + p...@13,1{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + p...@13,2{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + p...@13,3{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + p...@13,4{ + /config/("southbridge/amd/sb600/usb.dts"); + }; + p...@13,5{ + /config/("southbridge/amd/sb600/usb2.dts"); + }; + p...@14,0{ + /config/("southbridge/amd/sb600/sm.dts"); + }; + p...@14,1{ + /config/("southbridge/amd/sb600/ide.dts"); + }; + p...@14,2{ + /config/("southbridge/amd/sb600/ac97audio.dts"); + }; + p...@14,3{ + /config/("southbridge/amd/sb600/lpc.dts"); + iop...@2e { + /config/("superio/ite/it8712f/dts"); + com1enable = "1"; }; - pci4{ - /config/("southbridge/amd/sb600/hda.dts"); - }; - pci5{ - /config/("southbridge/amd/sb600/usb.dts"); - }; - pci6{ - /config/("southbridge/amd/sb600/usb2.dts"); - }; }; - p...@18,0 { - /config/("northbridge/amd/k8/pci"); + p...@14,4{ + /config/("southbridge/amd/sb600/pci.dts"); }; - p...@18,0 { + p...@18,0 { /config/("northbridge/amd/k8/pci"); - /* just for illustrating link #2 */ - p...@2,0{ - }; }; p...@18,1 {}; p...@18,2 {}; p...@18,3 {}; - iop...@2e { - /config/("superio/ite/it8712f/dts"); - com1enable = "1"; - }; }; }; Modified: coreboot-v3/mainboard/amd/serengeti/dts =================================================================== --- coreboot-v3/mainboard/amd/serengeti/dts 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/mainboard/amd/serengeti/dts 2009-01-08 16:22:39 UTC (rev 1109) @@ -22,76 +22,82 @@ device_operations="serengeti"; mainboard_vendor = "AMD"; mainboard_name = "Serengeti"; - subsystem_vendor = "PCI_VENDOR_ID_AMD"; - subsystem_device = "0x2b80"; + mainboard_pci_subsystem_vendor = "PCI_VENDOR_ID_AMD"; + mainboard_pci_subsystem_device = "0x2b80"; cpus { }; a...@0 { /config/("northbridge/amd/k8/apic"); }; dom...@0 { /config/("northbridge/amd/k8/domain"); - p...@18,0 { - /config/("northbridge/amd/k8/pci"); - pc...@0,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); - }; - pc...@0,1 { - /config/("southbridge/amd/amd8132/apic.dts"); - }; - pc...@1,0 { - /config/("southbridge/amd/amd8132/pcix.dts"); - }; - pc...@1,1 { - /config/("southbridge/amd/amd8132/apic.dts"); - }; - p...@0,0 { - /config/("southbridge/amd/amd8111/pci.dts"); - p...@0,0{ - /config/("southbridge/amd/amd8111/usb.dts"); - }; - p...@0,1{ - /config/("southbridge/amd/amd8111/usb.dts"); - }; - p...@0,2{ - /config/("southbridge/amd/amd8111/usb2.dts"); - disabled; - }; - p...@1,0{ - /config/("southbridge/amd/amd8111/nic.dts"); - disabled; - }; + pc...@0,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); }; - p...@1,0 { - /config/("southbridge/amd/amd8111/lpc.dts"); - iop...@2e { - /config/("superio/winbond/w83627hf/dts"); - kbenable = "1"; - com1enable = "1"; - hwmenable = "1"; - }; + pc...@0,1 { + /config/("southbridge/amd/amd8132/apic.dts"); }; - p...@1,1 { - /config/("southbridge/amd/amd8111/ide.dts"); - ide0_enable = "1"; - ide1_enable = "1"; + pc...@1,0 { + /config/("southbridge/amd/amd8132/pcix.dts"); }; - p...@1,2 { - /config/("southbridge/amd/amd8111/smbus.dts"); + pc...@1,1 { + /config/("southbridge/amd/amd8132/apic.dts"); }; - p...@1,3 { - /config/("southbridge/amd/amd8111/acpi.dts"); + p...@0,0 { + /config/("southbridge/amd/amd8111/pci.dts"); + p...@0,0{ + /config/("southbridge/amd/amd8111/usb.dts"); }; - p...@1,5 { - /config/("southbridge/amd/amd8111/ac97audio.dts"); + p...@0,1{ + /config/("southbridge/amd/amd8111/usb.dts"); + }; + p...@0,2{ + /config/("southbridge/amd/amd8111/usb2.dts"); disabled; }; - p...@1,6 { - /config/("southbridge/amd/amd8111/ac97modem.dts"); + p...@1,0{ + /config/("southbridge/amd/amd8111/nic.dts"); disabled; }; - p...@1,7 { + }; + p...@1,0 { + /config/("southbridge/amd/amd8111/lpc.dts"); + iop...@2e { + /config/("superio/winbond/w83627hf/dts"); + kbenable = "1"; + com1enable = "1"; + hwmenable = "1"; }; }; + p...@1,1 { + /config/("southbridge/amd/amd8111/ide.dts"); + ide0_enable = "1"; + ide1_enable = "1"; + }; + p...@1,2 { + /config/("southbridge/amd/amd8111/smbus.dts"); + }; + p...@1,3 { + /config/("southbridge/amd/amd8111/acpi.dts"); + }; + p...@1,5 { + /config/("southbridge/amd/amd8111/ac97audio.dts"); + disabled; + }; + p...@1,6 { + /config/("southbridge/amd/amd8111/ac97modem.dts"); + disabled; + }; + p...@1,7 { + }; + pc...@0,0 { + /config/("southbridge/amd/amd8151/agpbridge.dts"); + }; + pc...@1,0 { + /config/("southbridge/amd/amd8151/agpdev.dts"); + }; + p...@18,0 { + /config/("northbridge/amd/k8/pci"); + }; p...@18,1 {}; p...@18,2 {}; p...@18,3 { @@ -101,12 +107,6 @@ /config/("northbridge/amd/k8/pci"); }; p...@19,1 { - p...@0,0 { - /config/("southbridge/amd/amd8151/agpbridge.dts"); - }; - p...@1,0 { - /config/("southbridge/amd/amd8151/agpdev.dts"); - }; }; p...@19,2 {}; p...@19,3 { Modified: coreboot-v3/mainboard/gigabyte/m57sli/dts =================================================================== --- coreboot-v3/mainboard/gigabyte/m57sli/dts 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/mainboard/gigabyte/m57sli/dts 2009-01-08 16:22:39 UTC (rev 1109) @@ -44,20 +44,58 @@ a...@0 { }; dom...@0 { - p...@1,0{ + p...@0,0 { /* MCP55 RAM? */ }; + p...@1,0 { + /config/("southbridge/nvidia/mcp55/lpc.dts"); + iop...@2e { + /config/("superio/ite/it8716f/dts"); + com1enable = "1"; + ecenable = "1"; + kbenable = "1"; + mouseenable = "1"; + gpioenable = "1"; + }; + }; + p...@1,1 { /* smbus */ + }; + p...@2,0 { /* usb */ + }; + p...@2,1 { /* usb */ + }; + p...@4,0 { + /config/("southbridge/nvidia/mcp55/ide.dts"); + ide0_enable = "1"; + }; + p...@5,0 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + sata0_enable = "1"; + }; + p...@5,1 { + /config/("southbridge/nvidia/mcp55/sata.dts"); + sata1_enable = "1"; + }; + p...@6,0 { /* PCI */ + }; + p...@6,1 { + /*/config/("southbridge/nvidia/mcp55/audio.dts"); */ + }; + p...@8,0 { + /* + /config/("southbridge/nvidia/mcp55/nic.dts"); + mac_eeprom_smbus = "3"; + mac_eeprom_addr = "0x51"; + */ + }; + p...@f,0 { /* PCIe */ + }; p...@18,0 { /config/("northbridge/amd/k8/pci"); - p...@0,0 { - /config/("southbridge/nvidia/mcp55/ide.dts"); - }; - p...@0,1 { - /config/("southbridge/nvidia/mcp55/sata.dts"); - }; }; - iop...@2e { - /config/("superio/ite/it8716f/dts"); - com1enable = "1"; + p...@18,1 {}; + p...@18,2 {}; + p...@18,3 { + /config/("northbridge/amd/k8/mcf3"); }; }; }; Modified: coreboot-v3/northbridge/amd/k8/domain.c =================================================================== --- coreboot-v3/northbridge/amd/k8/domain.c 2009-01-08 16:19:51 UTC (rev 1108) +++ coreboot-v3/northbridge/amd/k8/domain.c 2009-01-08 16:22:39 UTC (rev 1109) @@ -717,6 +717,7 @@ { unsigned reg; int i; + struct device *last_dev, *children; printk(BIOS_DEBUG, "%s: %s \n", __func__, dev->dtsname); @@ -746,8 +747,31 @@ } } + /* Take processors off the list; we always know what link they're on. */ + for (last_dev = dev->link[0].children; last_dev; + last_dev = last_dev->sibling) + if (last_dev && last_dev->sibling == __f0_dev[0]) + last_dev->sibling = NULL; + max = amdk8_scan_chains(dev, __f0_dev[0], max); + /* Save non-processor children. */ + children = dev->link[0].children; + + /* Probe for processors and disable those that don't respond. */ + dev->link[0].children = __f0_dev[0]; + pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18,0), 0xff, 0); + + /* Add them back to the new end of the list. */ + for (last_dev = children; last_dev && last_dev->sibling; + last_dev = last_dev->sibling); + + if (last_dev) { + last_dev->sibling = __f0_dev[0]; + dev->link[0].children = children; + } else + dev->link[0].children = __f0_dev[0]; + return max; } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
