peOn Fri, Jan 9, 2009 at 10:40 AM, Peter Stuge <[email protected]> wrote: > Mart Raudsepp wrote: >> From 21de84bab3d32cefd71a2e95e6caf4f505c4cbff Mon Sep 17 00:00:00 2001 >> From: Mart Raudsepp <[email protected]> >> Date: Thu, 8 Jan 2009 20:49:16 +0200 >> Subject: [PATCH] cs5536: Add a NAND device and do the IDE PCI header >> disabling on time. >> >> This implements a nand device, akin to the ide device to follow the >> coreboot-v3 device tree design better. >> It allows us to do the IDE PCI header early enough in a clean way - the >> hide_vpci was called way too late >> before - in phase6 of southbridge device, but we need the Flash header >> active instead of IDE in the VSA2 >> before bus scans happen, or the PCI device gets disabled in coreboot >> understanding by the time we get it >> enabled in VSA2. >> It makes NAND setup work better, but still not completely. There is a VSA2 >> bug for which I made a patch, >> but waiting on a new binary to test if after that everything works or not. A >> quick hack to workaround the >> VSA2 bug suggests something further will still need fixing. There are also >> more potential opportunities >> to shuffle NAND code around to match v3 approach better, but that's a next >> step for me after NAND setup >> actually works right in the current form. >> >> Also corrected the documentation of ide_init() to match current reality. >> >> Signed-off-by: Mart Raudsepp <[email protected]> > > Acked-by: Peter Stuge <[email protected]> > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot > Peter already acked but for what it is worth.
Acked-by; Marc Jones <[email protected]> -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
