Here's a dump provided by Sven Schnelle <[email protected]> for the
ASUS A7M-266D (dual CPU) board with AMD-76x/AMD-780 chipset, for
reference and archival purposes.
There's some support in v1 for this, but as soon as the license patches
I sent are committed, I'll probably have a try at porting all of this
to v2 and adding support for the board.
-[0000:00]-+-00.0 Advanced Micro Devices [AMD] AMD-760 MP [IGD4-2P] System
Controller [1022:700c]
+-01.0-[0000:01]--
+-07.0 Advanced Micro Devices [AMD] AMD-768 [Opus] ISA [1022:7440]
+-07.1 Advanced Micro Devices [AMD] AMD-768 [Opus] IDE [1022:7441]
+-07.3 Advanced Micro Devices [AMD] AMD-768 [Opus] ACPI [1022:7443]
\-10.0-[0000:02]--+-00.0 Advanced Micro Devices [AMD] AMD-768
[Opus] USB [1022:7449]
+-04.0 C-Media Electronics Inc CM8738 [13f6:0111]
+-05.0 nVidia Corporation NV4 [RIVA TNT]
[10de:0020]
\-06.0 3Com Corporation 3c905 100BaseTX
[Boomerang] [10b7:9050]
-----------------------------------------------------------------------------------------------------
superiotool r3828
Probing for ALi Super I/O at 0x3f0...
Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
Failed. Returned data: id=0x3f3f, rev=0x3f
Probing for Fintek Super I/O at 0x2e...
Failed. Returned data: vid=0x80fe, id=0x5359
Probing for Fintek Super I/O at 0x4e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x2e...
Failed. Returned data: id=0x0000, rev=0x0
Probing for ITE Super I/O (init=it8761e) at 0x2e...
Failed. Returned data: id=0x0000, rev=0x0
Probing for ITE Super I/O (init=it8228e) at 0x2e...
Failed. Returned data: id=0x0000, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id=0x5953, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
Failed. Returned data: id=0x3f3f, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
Failed. Returned data: id=0x2222, rev=0x2
Probing for NSC Super I/O at 0x2e...
Failed. Returned data: port=0x00, port+1=0x00
Probing for NSC Super I/O at 0x4e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
Failed. Returned data: port=0xff, port+1=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
Failed. Returned data: id=0x22, rev=0x22
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
Failed. Returned data: id=0x22, rev=0x22
Probing for Winbond Super I/O (init=0x88) at 0x2e...
Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x89) at 0x2e...
Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
Failed. Returned data: id/oldid=0x00/0x00, rev=0x00
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Found Winbond W83627SF (id=0x59, rev=0x53) at 0x2e
No dump available for this Super I/O
Probing for Winbond Super I/O (init=0x88) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
Failed. Returned data: id/oldid=0x22/0x02, rev=0x22
Probing for Winbond Super I/O (init=0x89) at 0x370...
Failed. Returned data: id/oldid=0x22/0x02, rev=0x22
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
Failed. Returned data: id/oldid=0x22/0x02, rev=0x22
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
Failed. Returned data: id/oldid=0x22/0x02, rev=0x22
Probing for Winbond Super I/O (init=0x88) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
-----------------------------------------------------------------------------------
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
*/
#ifdef GETPIR
#include "pirq_routing.h"
#else
#include <arch/pirq_routing.h>
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*9, /* There can be total 9 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x1022, /* Vendor */
0x7440, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x17, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link,
bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x07<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02,
0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0},
{0x00,(0x08<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02,
0x1eb8}, {0x03, 0x1eb8}}, 0x1, 0x0},
{0x00,(0x09<<3)|0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03,
0x1eb8}, {0x00, 0x1eb8}}, 0x2, 0x0},
{0x02,(0x06<<3)|0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03,
0x1eb8}, {0x00, 0x1eb8}}, 0x3, 0x0},
{0x02,(0x05<<3)|0x0, {{0x02, 0x1eb8}, {0x03, 0x1eb8}, {0x00,
0x1eb8}, {0x01, 0x1eb8}}, 0x4, 0x0},
{0x02,(0x08<<3)|0x0, {{0x03, 0x1eb8}, {0x00, 0x1eb8}, {0x01,
0x1eb8}, {0x02, 0x1eb8}}, 0x5, 0x0},
{0x01,(0x05<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02,
0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0},
{0x02,(0x04<<3)|0x0, {{0x01, 0x1eb8}, {0x02, 0x1eb8}, {0x03,
0x1eb8}, {0x00, 0x1eb8}}, 0x0, 0x0},
{0x02,(0x00<<3)|0x0, {{0x00, 0x1eb8}, {0x01, 0x1eb8}, {0x02,
0x1eb8}, {0x03, 0x1eb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}
--------------------------------------------------------------------------------------------
/* generated by MPTable, version 2.0.15*/
/* as modified by RGM for coreboot */
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";
static const char productid[12] = "P4DPE ";
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
/*Bus: Bus ID Type*/
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 3, 0x20, res->base);
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 4, 0x20, res->base);
}
}
dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 5, 0x20, res->base);
}
}
dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 8, 0x20, res->base);
}
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x2, 0x3, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x2, 0x10, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x2, 0x14, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x2, 0x18, 0x2, 0x11);
smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x0, 0x2, 0x0);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x0, 0x2, 0x2);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x3, 0x2, 0x3);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x4, 0x2, 0x4);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x5, 0x2, 0x5);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x6, 0x2, 0x6);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x7, 0x2, 0x7);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x8, 0x2, 0x8);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0x9, 0x2, 0x9);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0xd, 0x2, 0xd);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT,
MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x3, 0xf, 0x2, 0xf);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
0x0, 0x0, MP_APIC_ALL, 0x1);
MP Config Extended Table Entries:
--
System Address Space
bus ID: 0 address type: I/O address
address base: 0x0
address range: 0x10000
--
System Address Space
bus ID: 0 address type: memory address
address base: 0x10000000
address range: 0xe9f00000
--
System Address Space
bus ID: 0 address type: prefetch address
address base: 0xf9f00000
address range: 0x4d00000
--
System Address Space
bus ID: 0 address type: memory address
address base: 0xfec00000
address range: 0x1400000
--
System Address Space
bus ID: 0 address type: memory address
address base: 0xa0000
address range: 0x20000
--
Bus Heirarchy
bus ID: 3 bus info: 0x01 parent bus ID: 0--
Compatibility Bus Address
bus ID: 0 address modifier: add
predefined range: 0x00000000--
Compatibility Bus Address
bus ID: 0 address modifier: add
predefined range: 0x00000001 /* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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