On 02.01.2009 16:37, Carl-Daniel Hailfinger wrote: > On 02.01.2009 16:24, Paul Menzel wrote: > >> Am Freitag, den 02.01.2009, 01:58 +0100 schrieb Peter Stuge: >> >> >>> Paul Menzel wrote: >>> >>> >>>> Done [1]. If you have time could you please send me or update the >>>> ROM chip package (PLCC, DIP32, DIP8, SOIC8)? >>>> >>>> >>> The board has a soldered PLCC LPC flash chip. >>> >>> >> Thanks, Peter. Done [1]. >> >> Unfortunately the Wiki seems to be an older version, since the links in >> the (change) comments are not formated correctly. At least it works in >> Wikipedia I think. Also references would be supported directly. >> >> Now it is up to Carl-Daniel to announce the port on the main page. >> >> > > Thanks, I'll test with 4 GB RAM and some USB flash drives and report back. >
4 GB are a problem for dualchannel because my DIMMS are only compatible and not identical. That's a missing feature in our code. I have sent a cleanup patch which should make fixing that a bit easier. Other status items were updated as well: Fan control and sensors do not work yet because the GPIO and SIO controls hang the machine during coreboot init if enabled via Config.lb. Maybe direct PNP writes will fix that. CPU frequency scaling works with the patch I sent a few hours ago. Besides that, I think the board is in pretty good shape. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
