Author: mjones Date: 2009-01-23 23:18:24 +0100 (Fri, 23 Jan 2009) New Revision: 1123
Modified: coreboot-v3/southbridge/amd/rs690/pcie.c Log: Fix rs690 bug about GPPSB configuration. Signed-off-by: Maggie Li <[email protected]> Reviewed-by: Zheng Bao <[email protected]> Acked-by: Marc Jones <[email protected]> Modified: coreboot-v3/southbridge/amd/rs690/pcie.c =================================================================== --- coreboot-v3/southbridge/amd/rs690/pcie.c 2009-01-23 10:53:55 UTC (rev 1122) +++ coreboot-v3/southbridge/amd/rs690/pcie.c 2009-01-23 22:18:24 UTC (rev 1123) @@ -135,8 +135,8 @@ /* sets desired GPPSB configurations, bit4-7 */ reg = nbmisc_read_index(nb_dev, 0x67); - reg &= 0xff0f; /* clean */ - reg |= cfg->gpp_configuration; + reg &= 0xffffff0f; /* clean */ + reg |= cfg->gpp_configuration << 4; nbmisc_write_index(nb_dev, 0x67, reg); /* read bit14 and write back its inverst value */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
