I sent this earlier, but for some reason it hasn't posted.. So sorry if its a
dup.
Has anyone tested the PIRQ table generator for the dbm690t?
I was running a minimal kernel ACPI off and IO_APIC off, and my interrupts were
not being assigned. The kernel found the PIRQ table, but that is all it did.
The PIRQ table being generated by the dbm690t, seems pretty simplistic compared
to the table I pulled from my BIOS. The one I pulled from my BIOS is reported
as having a CRC error when I try to use it. Something seems fishy.
The mpTable looks very similar to the one I pulled from my BIOS as I expected
it would. When my kernel is configured to use the mpTable, I am able to get to
a prompt. Interrupts are assigned WAY different when I use the mptable
generated from my BIOS, but they still work. I can find no relation between the
table and what interrupt is actually assigned.
ACPI seems to assign incorrect interrupts at random. Is it possible to dump an
ACPI table and reuse it?
I am able to boot all 3 ways with the original BIOS.
I have attached the mptable.c and irq_tables.c from the SOM-5781 690/600 board
I have been working on.
Thanks
Dan Lykowski
/* generated by MPTable, version 2.0.15*/
/* as modified by RGM for coreboot */
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "LNXI ";
static const char productid[12] = "P4DPE ";
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
/*Bus: Bus ID Type*/
smp_write_bus(mc, 0, "PCI ");
smp_write_bus(mc, 1, "PCI ");
smp_write_bus(mc, 2, "PCI ");
smp_write_bus(mc, 3, "PCI ");
smp_write_bus(mc, 4, "PCI ");
smp_write_bus(mc, 5, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 3, 0x20, res->base);
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 4, 0x20, res->base);
}
}
dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 5, 0x20, res->base);
}
}
dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 8, 0x20, res->base);
}
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4c, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4d, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4e, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4d, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4e, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x4f, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x50, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x15, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x14, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0x0, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x0, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x48, 0x2, 0x16);
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x0, 0x2, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x0, 0x2, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x3, 0x2, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x4, 0x2, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x6, 0x2, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x7, 0x2, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x5, 0x8, 0x2, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0x9, 0x2, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0xc, 0x2, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0xd, 0x2, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x5, 0xf, 0x2, 0xf);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0);
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
unsigned long write_smp_table(unsigned long addr)
{
void *v;
v = smp_write_floating_table(addr);
return (unsigned long)smp_write_config_table(v);
}
/* This file was generated by getpir.c, do not modify!
* (but if you do, please run checkpir on it to verify)
*
* Contains the IRQ Routing Table dumped directly from your
* memory, which BIOS sets up.
*
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
*/
#ifdef GETPIR
#include "pirq_routing.h"
#else
#include <arch/pirq_routing.h>
#endif
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*15, /* There can be total 15 devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x00<<3)|0x0, /* Where the interrupt router lies (dev) */
0xc20, /* IRQs devoted exclusively to PCI usage */
0, /* Vendor */
0, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0x32, /* u8 checksum. This has to be set to some
value that would give 0 after the sum of all
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x02<<3)|0x0, {{0x03, 0xdcb8}, {0x03, 0xdcb8}, {0x03, 0xdcb8}, {0x03, 0xdcb8}}, 0x1, 0x0},
{0x00,(0x03<<3)|0x0, {{0x04, 0xdcb8}, {0x04, 0xdcb8}, {0x04, 0xdcb8}, {0x04, 0xdcb8}}, 0x2, 0x0},
{0x00,(0x04<<3)|0x0, {{0x01, 0xdcb8}, {0x01, 0xdcb8}, {0x01, 0xdcb8}, {0x01, 0xdcb8}}, 0x3, 0x0},
{0x00,(0x06<<3)|0x0, {{0x03, 0xdcb8}, {0x03, 0xdcb8}, {0x03, 0xdcb8}, {0x03, 0xdcb8}}, 0x4, 0x0},
{0x00,(0x07<<3)|0x0, {{0x04, 0xdcb8}, {0x04, 0xdcb8}, {0x04, 0xdcb8}, {0x04, 0xdcb8}}, 0x5, 0x0},
{0x00,(0x08<<3)|0x0, {{0x01, 0xdcb8}, {0x01, 0xdcb8}, {0x01, 0xdcb8}, {0x01, 0xdcb8}}, 0x6, 0x0},
{0x01,(0x05<<3)|0x0, {{0x03, 0xdcb8}, {0x04, 0xdcb8}, {0x01, 0xdcb8}, {0x02, 0xdcb8}}, 0x7, 0x0},
{0x04,(0x04<<3)|0x0, {{0x05, 0xdcb8}, {0x05, 0xdcb8}, {0x05, 0xdcb8}, {0x05, 0xdcb8}}, 0x8, 0x0},
{0x04,(0x05<<3)|0x0, {{0x06, 0xdcb8}, {0x07, 0xdcb8}, {0x08, 0xdcb8}, {0x05, 0xdcb8}}, 0x9, 0x0},
{0x04,(0x06<<3)|0x0, {{0x07, 0xdcb8}, {0x08, 0xdcb8}, {0x05, 0xdcb8}, {0x06, 0xdcb8}}, 0xa, 0x0},
{0x04,(0x07<<3)|0x0, {{0x08, 0xdcb8}, {0x05, 0xdcb8}, {0x06, 0xdcb8}, {0x07, 0xdcb8}}, 0xb, 0x0},
{0x00,(0x01<<3)|0x0, {{0x03, 0xdcb8}, {0x04, 0xdcb8}, {0x01, 0xdcb8}, {0x02, 0xdcb8}}, 0x0, 0x0},
{0x00,(0x13<<3)|0x0, {{0x01, 0xdcb8}, {0x02, 0xdcb8}, {0x03, 0xdcb8}, {0x04, 0xdcb8}}, 0x0, 0x0},
{0x00,(0x12<<3)|0x0, {{0x07, 0xdcb8}, {0x07, 0xdcb8}, {0x07, 0xdcb8}, {0x07, 0xdcb8}}, 0x0, 0x0},
{0x00,(0x14<<3)|0x0, {{0x01, 0xdcb8}, {0x02, 0xdcb8}, {0x03, 0xdcb8}, {0x04, 0xdcb8}}, 0x0, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr);
}
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