On Fri, Feb 06, 2009 at 11:50:26PM +0100, Stefan Reinauer wrote: > ron minnich wrote: > > Stepan can tell us, since he has working smm on kontron, but I can not > > believe smm can not be cached. > Occasionally a CPU might do speculative readahead on the SMRAM memory > while not in SMM. The chipset will generate master aborts on the PCI > bus, so the cached data is incorrect (0xff) and upon SMM entry the CPU > goes to nirvana. The SMM area in ASEG is always uncached. The upper > SMRAM areas can be cached, but they must only be cached while in SMM.
If there is memory only accessible from SMM mode, then I agree it would need to be uncached. I thought that Jason was just reserving memory for use by SMM - memory that could also be read/written in non-SMM mode. In that case, I did not think caching needed to be disabled. Indeed, the intel system programming guide recommends using some cached memory for SMM. -Kevin Random thought - I wonder if the OS could "break into" SMM mode by turning on caching for the SMM area and then manipulating the cache contents so that an SMI used icache/dcache contents set by the OS. -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
