Author: myles Date: 2009-02-09 18:52:54 +0100 (Mon, 09 Feb 2009) New Revision: 3931
Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c trunk/coreboot-v2/src/arch/i386/boot/tables.c trunk/coreboot-v2/src/arch/i386/lib/cpu.c trunk/coreboot-v2/src/arch/i386/lib/exception.c trunk/coreboot-v2/src/arch/i386/smp/mpspec.c trunk/coreboot-v2/src/boot/elfboot.c trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c trunk/coreboot-v2/src/devices/device_util.c trunk/coreboot-v2/src/devices/pci_device.c trunk/coreboot-v2/src/devices/pci_rom.c trunk/coreboot-v2/src/devices/pnp_device.c trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c Log: Remove some warnings, mainly from format strings which didn't match the arguments. Signed-off-by: Myles Watson <[email protected]> Acked-by: Peter Stuge <[email protected]> Modified: trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -251,7 +251,7 @@ head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes); head->header_checksum = 0; head->header_checksum = compute_ip_checksum(head, sizeof(*head)); - printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n", + printk_debug("Wrote coreboot table at: %p - %p checksum %x\n", head, rec, head->table_checksum); return (unsigned long)rec; } @@ -415,16 +415,16 @@ low_table_end = (unsigned long)head; } - printk_debug("Adjust low_table_end from 0x%08x to ", low_table_end); + printk_debug("Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned low_table_end &= ~0xfff; - printk_debug("0x%08x \n", low_table_end); + printk_debug("0x%08lx \n", low_table_end); /* The Linux kernel assumes this region is reserved */ - printk_debug("Adjust rom_table_end from 0x%08x to ", rom_table_end); + printk_debug("Adjust rom_table_end from 0x%08lx to ", rom_table_end); rom_table_end += 0xffff; // 64K align rom_table_end &= ~0xffff; - printk_debug("0x%08x \n", rom_table_end); + printk_debug("0x%08lx \n", rom_table_end); #if (HAVE_OPTION_TABLE == 1) { Modified: trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/boot/pirq_routing.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -91,7 +91,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Copying Interrupt Routing Table to 0x%08x... ", addr); + printk_info("Copying Interrupt Routing Table to 0x%08lx... ", addr); memcpy((void *)addr, &intel_irq_routing_table, intel_irq_routing_table.size); printk_info("done.\n"); verify_copy_pirq_routing_table(addr); Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -92,7 +92,7 @@ mpc_start &= ~1023; rom_table_start = mpc_start; } - printk_debug("move mptable from 0x%0x to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size); + printk_debug("move mptable from 0x%0lx to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size); memcpy((unsigned char *)mpc_start, (unsigned char *)low_table_end, mptable_size); smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start); memset((unsigned char *)low_table_end, '\0', mptable_size); Modified: trunk/coreboot-v2/src/arch/i386/lib/cpu.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/lib/cpu.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -225,7 +225,7 @@ info = cpu_info(); - printk_notice("Initializing CPU #%d\n", info->index); + printk_notice("Initializing CPU #%ld\n", info->index); cpu = info->cpu; if (!cpu) { @@ -261,7 +261,7 @@ cpu->ops->init(cpu); } - printk_info("CPU #%d initialized\n", info->index); + printk_info("CPU #%ld initialized\n", info->index); return; } Modified: trunk/coreboot-v2/src/arch/i386/lib/exception.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/lib/exception.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/lib/exception.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -481,10 +481,10 @@ } #else /* !CONFIG_GDB_STUB */ printk_emerg( - "Unexpected Exception: %d @ %02x:%08lx - Halting\n" - "Code: %d eflags: %08lx\n" - "eax: %08lx ebx: %08lx ecx: %08lx edx: %08lx\n" - "edi: %08lx esi: %08lx ebp: %08lx esp: %08lx\n", + "Unexpected Exception: %d @ %02x:%08x - Halting\n" + "Code: %d eflags: %08x\n" + "eax: %08x ebx: %08x ecx: %08x edx: %08x\n" + "edi: %08x esi: %08x ebp: %08x esp: %08x\n", info->vector, info->cs, info->eip, info->error_code, info->eflags, info->eax, info->ebx, info->ecx, info->edx, Modified: trunk/coreboot-v2/src/arch/i386/smp/mpspec.c =================================================================== --- trunk/coreboot-v2/src/arch/i386/smp/mpspec.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/arch/i386/smp/mpspec.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -236,7 +236,7 @@ if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { /* pci device */ - printk_debug("route irq: %s %04x\n", dev_path(child)); + printk_debug("route irq: %s\n", dev_path(child)); for (i = 0; i < 4; i++) smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]); goto next; @@ -246,7 +246,7 @@ case PCI_CLASS_BRIDGE_PCI: case PCI_CLASS_BRIDGE_PCMCIA: case PCI_CLASS_BRIDGE_CARDBUS: - printk_debug("route irq bridge: %s %04x\n", dev_path(child)); + printk_debug("route irq bridge: %s\n", dev_path(child)); smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x); } Modified: trunk/coreboot-v2/src/boot/elfboot.c =================================================================== --- trunk/coreboot-v2/src/boot/elfboot.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/boot/elfboot.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -76,7 +76,7 @@ memcpy(n_desc, buff, 2); } if (checksum != cb->ip_checksum) { - printk_err("Image checksum: %04x != computed checksum: %04x\n", + printk_err("Image checksum: %04x != computed checksum: %04lx\n", cb->ip_checksum, checksum); } return checksum == cb->ip_checksum; @@ -500,7 +500,7 @@ /* Zero the extra bytes between middle & end */ if (middle < end) { printk_debug("Clearing Segment: addr: 0x%016lx memsz: 0x%016lx\n", - (unsigned long)middle, end - middle); + (unsigned long)middle, (unsigned long)(end - middle)); /* Zero the extra bytes */ memset(middle, 0, end - middle); @@ -590,7 +590,7 @@ /* Reset to booting from this image as late as possible */ boot_successful(); - printk_debug("Jumping to boot code at 0x%x\n", entry); + printk_debug("Jumping to boot code at 0x%p\n", entry); post_code(0xfe); /* Jump to kernel */ Modified: trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/amd/model_fxx/model_fxx_init.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -231,7 +231,7 @@ size = (limitk - basek) << 10; addr = map_2M_page(basek >> 11); if (addr == MAPPING_ERROR) { - printk_err("Cannot map page: %x\n", basek >> 11); + printk_err("Cannot map page: %lx\n", basek >> 11); return; } @@ -312,7 +312,7 @@ begink = CONFIG_LB_MEM_TOPK; } - printk_debug("Clearing memory %uK - %uK: ", begink, endk); + printk_debug("Clearing memory %luK - %luK: ", begink, endk); /* Save the normal state */ save_mtrr_state(&mtrr_state); @@ -465,7 +465,9 @@ extern void model_fxx_update_microcode(unsigned cpu_deviceid); int init_processor_name(void); +#if CONFIG_USBDEBUG_DIRECT static unsigned ehci_debug_addr; +#endif void model_fxx_init(device_t dev) { Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -55,7 +55,7 @@ LAPIC_DELIVERY_MODE_NMI) ); - printk_debug(" apic_id: 0x%02x ", lapicid()); + printk_debug(" apic_id: 0x%02lx ", lapicid()); #else /* !NEED_LLAPIC */ /* Only Pentium Pro and later have those MSR stuff */ Modified: trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/x86/lapic/lapic_cpu_init.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -85,14 +85,14 @@ send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %d: First apic write timed out. Disabling\n", + printk_err("CPU %ld: First apic write timed out. Disabling\n", apicid); // too bad. - printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR)); + printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk_err("Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR)); + printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } @@ -114,7 +114,7 @@ send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %d: Second apic write timed out. Disabling\n", + printk_err("CPU %ld: Second apic write timed out. Disabling\n", apicid); // too bad. return 0; @@ -345,8 +345,6 @@ /* C entry point of secondary cpus */ void secondary_cpu_init(void) { - unsigned long cpunum; - atomic_inc(&active_cpus); #if SERIAL_CPU_INIT == 1 #if CONFIG_MAX_CPUS>2 Modified: trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c =================================================================== --- trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/cpu/x86/mtrr/mtrr.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -241,7 +241,7 @@ align = max_align; } sizek = 1 << align; - printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n", + printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": ((type==MTRR_TYPE_WRBACK)?"WB":"Other") Modified: trunk/coreboot-v2/src/devices/device_util.c =================================================================== --- trunk/coreboot-v2/src/devices/device_util.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/device_util.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -467,7 +467,7 @@ #endif } printk_debug( - "%s %02x <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n", + "%s %02lx <- [0x%010Lx - 0x%010Lx] size 0x%08Lx gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, base, end, Modified: trunk/coreboot-v2/src/devices/pci_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_device.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/pci_device.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -207,7 +207,7 @@ if (moving == 0) { if (value != 0) { printk_debug( - "%s register %02x(%08x), read-only ignoring it\n", + "%s register %02lx(%08lx), read-only ignoring it\n", dev_path(dev), index, value); } resource->flags = 0; @@ -311,7 +311,7 @@ if (moving == 0) { if (value != 0) { - printk_debug("%s register %02x(%08x), read-only ignoring it\n", + printk_debug("%s register %02lx(%08lx), read-only ignoring it\n", dev_path(dev), index, value); } resource->flags = 0; @@ -459,7 +459,7 @@ /* Make certain the resource has actually been set */ if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n", + printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); @@ -546,7 +546,7 @@ else { /* Don't let me think I stored the resource */ resource->flags &= ~IORESOURCE_STORED; - printk_err("ERROR: invalid resource->index %x\n", + printk_err("ERROR: invalid resource->index %lx\n", resource->index); } report_resource_stored(dev, resource, ""); Modified: trunk/coreboot-v2/src/devices/pci_rom.c =================================================================== --- trunk/coreboot-v2/src/devices/pci_rom.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/pci_rom.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -45,7 +45,7 @@ return NULL; } - printk_debug("rom address for %s = %x\n", dev_path(dev), rom_address); + printk_debug("rom address for %s = %lx\n", dev_path(dev), rom_address); if(!dev->on_mainboard) { /* enable expansion ROM address decoding */ @@ -110,12 +110,12 @@ extern device_t vga_pri; // the primary vga device, defined in device.c if (dev != vga_pri) return NULL; // only one VGA supported #endif - printk_debug("copying VGA ROM Image from 0x%x to 0x%x, 0x%x bytes\n", + printk_debug("copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n", rom_header, PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } else { - printk_debug("copying non-VGA ROM Image from 0x%x to 0x%x, 0x%x bytes\n", + printk_debug("copying non-VGA ROM Image from %p to %p, 0x%x bytes\n", rom_header, pci_ram_image_start, rom_size); memcpy(pci_ram_image_start, rom_header, rom_size); pci_ram_image_start += rom_size; Modified: trunk/coreboot-v2/src/devices/pnp_device.c =================================================================== --- trunk/coreboot-v2/src/devices/pnp_device.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/devices/pnp_device.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -103,7 +103,7 @@ static void pnp_set_resource(device_t dev, struct resource *resource) { if (!(resource->flags & IORESOURCE_ASSIGNED)) { - printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n", + printk_err("ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", dev_path(dev), resource->index, resource_type(resource), resource->size); @@ -121,7 +121,7 @@ pnp_set_irq(dev, resource->index, resource->base); } else { - printk_err("ERROR: %s %02x unknown resource type\n", + printk_err("ERROR: %s %02lx unknown resource type\n", dev_path(dev), resource->index); return; } Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c =================================================================== --- trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/mainboard/tyan/s2895/irq_tables.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -72,7 +72,7 @@ addr &= ~15; /* This table must be betweeen 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk_info("Writing IRQ routing tables to 0x%lx...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -314,7 +314,7 @@ continue; base = res->base; end = resource_end(res); - printk_debug("ck804 lpc decode:%s, base=0x%08x, end=0x%08x\r\n", dev_path(child), base, end); + printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end); switch (base) { case 0x3f8: // COM1 reg |= (1 << 0); Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2009-02-05 02:18:42 UTC (rev 3930) +++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_sata.c 2009-02-09 17:52:54 UTC (rev 3931) @@ -11,6 +11,7 @@ #include <device/pci_ops.h> #include "ck804.h" +#if CK804_SATA_RESET_FOR_ATAPI static void sata_com_reset(struct device *dev, unsigned reset) // reset = 1 : reset // reset = 0 : clear @@ -21,7 +22,7 @@ base = (uint32_t *) pci_read_config32(dev, 0x24); - printk_debug("base = %08x\r\n", base); + printk_debug("base = %08lx\n", base); if (reset) { *(base + 4) = 0xffffffff; @@ -71,6 +72,7 @@ printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword); } } +#endif static void sata_init(struct device *dev) { @@ -132,7 +134,7 @@ dword |= 2; pci_write_config32(dev, 0xf8, dword); -#if 0 +#if CK804_SATA_RESET_FOR_ATAPI dword = pci_read_config32(dev, 0xac); dword &= ~((1 << 13) | (1 << 14)); dword |= (1 << 13) | (0 << 14); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
