> -----Original Message----- > From: Kevin O'Connor [mailto:[email protected]] > Sent: Wednesday, February 18, 2009 8:31 PM > To: Myles Watson > Cc: [email protected] > Subject: Re: [coreboot] slow load times > > On Wed, Feb 18, 2009 at 07:51:33PM -0700, Myles Watson wrote: > > > > > #define CONFIG_OPTIONROMS_DEPLOYED 0 > > > > Maybe we should modify buildrom so that this is the default when using > > SeaBIOS. > > I think we should. > > > > The current code is in src/pci.h in the foreachpci macro and in > > > src/pci.c in the pci_next() function. If there is a better way to > > > scan, please let me know. > > > > It's a fine way to scan. The problem is that there is no logical > connection > > from bus 0 to bus 0x40 on my machine. It happens because there are > multiple > > links on the Opterons. For desktop machines, many times there is only > one > > link that goes to the chipset, but servers and workstations sometimes > have > > more. > > Well, that's a pain. Yes.
> I'm surprised they didn't just put a dummy > bridge entry on bus 0 that points to bus 0x40 -- it'd make scanning > easier. Part of the problem is that some of the buses are there only when the second Opteron is installed. Nothing can be simple :) You can read the Opteron's registers to know which other buses there are, and the Opterons are always on bus 0. It's just not a general solution. > > You could change the pciforeach macro from: > > for (MAX=0x0100, BDF=pci_next(0, &MAX) \ > > to: > > for (MAX=0x4000, BDF=pci_next(0, &MAX) \ For my own use I can hard code something pretty easily. The general case is much harder. Thanks, Myles -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
