On Fri, Feb 20, 2009 at 11:47 AM, Mart Raudsepp <[email protected]> wrote: > On T, 2009-02-17 at 15:01 +0200, Mart Raudsepp wrote: >> cs5536: Make NAND code optional and implement timing setting >> >> The reset value for NAND timings is the slowest possible for Flash interface. >> Implement optionally setting it to a different value inside the NAND device. >> Set it to appropriate values for Artec Group DBE61 and DBE62. >> This results in a roughly two times quicker read time as measured by hdparm >> for these boards. >> >> Because we can not cast to southbridge_amd_cs5536_nand_config if the board >> dts >> does not have an entry for the NAND device, this change proposes a method for >> reasonably clean way to only optionally compile in support for certain >> devices: >> If a board wants to support an optional device, its Kconfig entry can select >> that configuration. If it's optional even across the same board, it can >> expose >> a subconfig option of the board, that describes it and if chosen selects the >> device config. The source code for that device is conditionally compiled only >> if the Kconfig option gets enabled by the configuration for the board. >> A requirement is that if the board configuration can enable a device, it is >> contained in the boards dts file as well. >> >> A perhaps better long-term alternative for this could be making dtc generate >> preprocessor definitions for each device_configuration struct that it >> creates. >> Then the source code file is always enabled, but that file can be wrapped >> around a simple #ifdef check in its entirety. >> >> Conversion to the alternative approach from the short-term Kconfig approach >> proposed here should be relatively easy, as to not block inclusion of the >> Kconfig approach in the short term. >> >> Signed-off-by: Mart Raudsepp <[email protected]> > > > Any comments, acks, rejections, anything? :)
I think it looks good but can you attach the patch instead of inline? Pulling it from inline is hard to apply. Marc -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
