This patch makes several CMOS variable reads dependent on whether
there's a table to read. Otherwise you never know what you'll get
from the factory BIOS. There are probably more, but these are the
ones compiled into the s2895.
Signed-off-by: Myles Watson <[email protected]>
Thanks,
Myles
Index: svn/src/cpu/amd/dualcore/dualcore.c
===================================================================
--- svn.orig/src/cpu/amd/dualcore/dualcore.c
+++ svn/src/cpu/amd/dualcore/dualcore.c
@@ -56,8 +56,9 @@ static inline void start_other_cores(voi
unsigned nodes;
unsigned nodeid;
- if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
- return;
+ if (HAVE_OPTION_TABLE &&
+ read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) {
+ return; // disable dual_core
}
nodes = get_nodes();
Index: svn/src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- svn.orig/src/cpu/amd/model_fxx/init_cpus.c
+++ svn/src/cpu/amd/model_fxx/init_cpus.c
@@ -72,7 +72,7 @@ static void for_each_ap(unsigned bsp_api
nodes = get_nodes();
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS == 1 && HAVE_OPTION_TABLE == 1
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core
disable_siblings = 1;
}
Index: svn/src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/coherent_ht.c
+++ svn/src/northbridge/amd/amdk8/coherent_ht.c
@@ -1597,7 +1597,8 @@ static void coherent_ht_finalize(unsigne
#if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus;
- if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
+ if ((!HAVE_OPTION_TABLE) ||
+ read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
total_cpus = verify_dualcore(nodes);
}
else {
Index: svn/src/northbridge/amd/amdk8/raminit.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/raminit.c
+++ svn/src/northbridge/amd/amdk8/raminit.c
@@ -598,11 +598,11 @@ static void hw_enable_ecc(const struct m
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
- if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+ if (HAVE_OPTION_TABLE &&
+ read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn;
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
-
}
static int is_dual_channel(const struct mem_controller *ctrl)
@@ -1146,7 +1146,8 @@ static void order_dimms(const struct mem
{
unsigned long tom_k, base_k;
- if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+ if ((!HAVE_OPTION_TABLE) ||
+ read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl);
} else {
print_debug("Interleaving disabled\r\n");
@@ -1450,7 +1451,7 @@ static struct spd_set_memclk_result spd_
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
- if (bios_cycle_time > min_cycle_time) {
+ if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
min_latency = 2;
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
