It seems like these two snippets should be related in some way. Do
you have to set them equal?
Index: src/config/Options.lb
===================================================================
--- src/config/Options.lb (.../branches/upstream/coreboot-v2)
+++ src/config/Options.lb (.../trunk/coreboot-v2)
@@ -983,6 +983,13 @@
comment "enable mmconfig for pci conf"
end
+define MMCONF_BASE_ADDRESS
+ default none
+ format "0x%x"
+ export used
+ comment "enable mmconfig base address"
+end
+
from /src/northbridge/intel/i945/northbridge.c:
/* We use 0xcf as an unused index for our PCIe bar so that we find it
again */
resource = new_resource(dev, 0xcf);
resource->base = DEFAULT_PCIEXBAR;
resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config
space */
resource->flags =
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
resource->base, (resource->base + resource->size));
I didn't see anywhere that you enabled the PCI decode space in the
fam10 code. Is it fixed? How does resource allocation avoid it?
Thanks,
Myles
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