-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello,
To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region. This is last missing bit to make SeaBIOS & Windows happy ;) This patch depends on the small patch adding the HAVE_HIGH_TABLES to K8 NB by Myles. Windows 7 still boots ;) once this is in, we have no need for other patches. Signed-off-by: Rudolf Marek <[email protected]> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkm1pRgACgkQ3J9wPJqZRNXOfQCePVAeWWHJBNIf96NseAH+E2HY 9JsAoKuanbUTqaY/1KyhVaTci3PHUvbd =nzql -----END PGP SIGNATURE-----
Index: coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-03-09 22:08:24.800422656 +0100
+++ coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-03-09 23:54:03.673421249 +0100
@@ -21,8 +21,22 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <boot/tables.h>
#include "chip.h"
+/* in arch/i386/boot/tables.c */
+extern uint64_t high_tables_base, high_tables_size;
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+#if HAVE_HIGH_TABLES == 1
+ printk_debug("Adding high table area\n");
+ lb_add_memory_range(mem, LB_MEM_TABLE,
+ high_tables_base, high_tables_size);
+#endif
+ return 0;
+}
+
#if CONFIG_CHIP_NAME == 1
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS M2V-MX SE Mainboard")
Index: coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/m2v-mx_se/Options.lb 2009-03-09 22:12:50.037420967 +0100
+++ coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-03-09 22:30:15.180421022 +0100
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright (C) 2007 Rudolf Marek <[email protected]>
+## Copyright (C) 2007, 2009 Rudolf Marek <[email protected]>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License v2 as published by
@@ -44,8 +44,11 @@
uses STACK_SIZE
uses HEAP_SIZE
# uses USE_OPTION_TABLE
-# uses CONFIG_LB_MEM_TOPK
+uses CONFIG_LB_MEM_TOPK
uses HAVE_ACPI_TABLES
+uses HAVE_MAINBOARD_RESOURCES
+uses HAVE_HIGH_TABLES
+uses HAVE_LOW_TABLES
uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END
uses LB_CKS_LOC
@@ -110,6 +113,10 @@
default CONFIG_MAX_PHYSICAL_CPUS = 1
default CONFIG_LOGICAL_CPUS = 1
default HAVE_ACPI_TABLES = 1
+default HAVE_MAINBOARD_RESOURCES = 1
+default HAVE_HIGH_TABLES = 1
+default HAVE_LOW_TABLES = 0
+
# default CONFIG_CHIP_NAME = 1
# 1G memory hole
@@ -152,8 +159,9 @@
default STACK_SIZE = 8 * 1024
default HEAP_SIZE = 256 * 1024
# More 1M for pgtbl.
-# default CONFIG_LB_MEM_TOPK = 2048
-default _RAMBASE = 0x00004000
+default CONFIG_LB_MEM_TOPK = 2048
+# to 1MB
+default _RAMBASE = 0x100000
# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
default CONFIG_ROM_PAYLOAD = 1
default CC = "$(CROSS_COMPILE)gcc -m32"
Index: coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
===================================================================
--- coreboot-v2.orig/src/mainboard/asus/m2v-mx_se/Config.lb 2009-03-09 22:16:51.768422759 +0100
+++ coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-03-09 22:18:05.149421256 +0100
@@ -34,7 +34,8 @@
default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
##WARNING enable caching of whole ROM during CAR
-default XIP_ROM_SIZE = ROM_SIZE
+##for 512KB flash
+default XIP_ROM_SIZE = 0x80000
default XIP_ROM_BASE = 0xffffffff + 1 - XIP_ROM_SIZE
arch i386 end
Index: coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c
===================================================================
--- coreboot-v2.orig/src/southbridge/via/k8t890/k8t890_dram.c 2009-03-09 22:47:02.428422172 +0100
+++ coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c 2009-03-09 23:02:04.773420857 +0100
@@ -91,6 +91,17 @@
(proposed_base < ((uint64_t) 0xffffffff) )) {
resmax = res;
}
+#if HAVE_HIGH_TABLES==1
+/* in arch/i386/boot/tables.c */
+extern uint64_t high_tables_base, high_tables_size;
+
+ if ((high_tables_base) && ((high_tables_base > proposed_base) &&
+ (high_tables_base < (res->base + res->size)))) {
+ high_tables_base = proposed_base - high_tables_size;
+ printk_debug("Moving the high_tables_base pointer to "
+ "new base %llx\n", high_tables_base);
+ }
+#endif
}
fixes.patch.sig
Description: Binary data
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
