This is the state of my v2 tree with Asus M2A-VM support. The patch is
against the AMD DBM690T, so you have to compile the amd/dbm690t target
for your Asus M2A-VM.
Notes:
- If you want a working NIC, revert the part enabling MMCONFIG in
LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c.
- If you want a working NIC and ACPI support for SATA, go to
LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl and
enable the SB5 EVIL HACK and comment out the active
"OperationRegion(SB5..." instead.
- Thermal setup is wrong.
- More than 2 GB RAM will not work (SATA will hang).
- FILO will usually work. Sometimes, you may have to poke the reset
button first.
Suggestions:
- Revert the MMCONFIG stuff. Ignore ACPI for SATA.
Signed-off-by: Carl-Daniel Hailfinger <[email protected]>
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
(Arbeitskopie)
@@ -63,8 +63,8 @@
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
- /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr,
dev->bus->secondary,
- dev->path.pci.devfn);*/
+ printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr,
dev->bus->secondary,
+ dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
dev->path.pci.devfn << 12 | reg_pos;
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Arbeitskopie)
@@ -195,7 +195,7 @@
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not
supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
- chip cpu/amd/socket_S1G1
+ chip cpu/amd/socket_AM2
device apic 0 on end
end
end
@@ -211,7 +211,7 @@
end
end
device pci 2.0 on end # PCIE P2P bridge
(external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P
bridge 0x791b
+ #device pci 3.0 off end # PCIE P2P
bridge 0x791b
device pci 4.0 on end # PCIE P2P bridge
0x7914
device pci 5.0 on end # PCIE P2P bridge
0x7915
device pci 6.0 on end # PCIE P2P bridge
0x7916
@@ -255,9 +255,9 @@
device pci 14.3 on # LPC 0x438d
chip superio/ite/it8712f
device pnp 2e.0 off #
Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
+ #io 0x60 = 0x3f0
+ #irq 0x70 = 6
+ #drq 0x74 = 2
end
device pnp 2e.1 on #
Com1
io 0x60 = 0x3f8
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
(Arbeitskopie)
@@ -54,7 +54,7 @@
extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
+extern u32 sbdn_sb600;
unsigned long write_pirq_routing_table(unsigned long addr)
{
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
(Arbeitskopie)
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-static void setup_dbm690t_resource_map(void)
+static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which
contain the enables */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
(Arbeitskopie)
@@ -33,8 +33,8 @@
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
+ Name(PBAD, 0xFFF00000) /* Address of BIOS area (If TOM2 != 0, Addr >>
16) */
+ Name(PBLN, 0x00100000) /* Length of BIOS area (1 MB hardcoded) */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
@@ -273,7 +273,7 @@
* The 8 comes from 8 functions per device, and 4096
bytes per function config space
*/
Offset(0x00090024), /* Byte offset to SATA register
24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
+ STB5, 32, /* Address of SATA_BAR5 */
Offset(0x00098042), /* Byte offset to OHCI0
register 42h - Bus 0, Device 19, Function 0 */
PT0D, 1,
PT1D, 1,
@@ -297,7 +297,9 @@
P92E, 1, /* Port92 decode enable */
}
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ /* FIXME: EVIL HACK. SB5 address is hardcoded to 0xfc409000 in
the hope the OS won't touch it. */
+ /*OperationRegion(SB5, SystemMemory, 0xfc409000, 0x1000)*/ /*
SATA_BAR5 (ABAR) */
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000) /* SATA_BAR5
(ABAR) */
Field(SB5, AnyAcc, NoLock, Preserve)
{
/* Port 0 */
@@ -308,9 +310,9 @@
, 3,
P0BY, 1,
Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
+ P0DD, 4, /* Port 0 Device Detection
(DET) */
, 4,
- P0IS, 4,
+ P0IS, 4, /* Port 0 Interface Power
Management (IPM) */
Offset(0x12C), /* Port 0 Serial ATA control */
P0DI, 4,
Offset(0x130), /* Port 0 Serial ATA error */
@@ -1493,23 +1495,24 @@
Memory32Fixed(READONLY, 0x000E0000, 0x00020000,
RDBS) /* BIOS ROM area */
/* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)
/* 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)
/* 1MB to TopMem, the length is filled out when DMLL is calculated */
/* BIOS space just below 4GB */
DWORDMemory(
ResourceProducer, PosDecode, MinFixed,
MaxFixed, Cacheable, ReadWrite,
0x00, /* Granularity
*/
0x00000000, /* Min */
- 0x00000000, /* Max */
+ 0xFFFFFFFF, /* Max */
0x00000000, /* Translation
*/
0x00000000, /* Max-Min,
RLEN */
,,
- PCBM
+ PCBM,
+ AddressRangeReserved
)
/* DRAM memory from 4GB to TopMem2 */
QWORDMemory(ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity
*/
+ 0x3FFFFFFF, /* Granularity
must be 1 GB or lower! Due to hoisting, RLEN will always be 2k+1 GB */
0x00000000, /* Min */
0x00000000, /* Max */
0x00000000, /* Translation
*/
@@ -1543,6 +1546,7 @@
CreateQWordField(CRES, ^DMHI._MIN, DMHB)
CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^DMHI._MAX, DMHM)
CreateQWordField(CRES, ^PEBM._MIN, EBMB)
CreateQWordField(CRES, ^PEBM._LEN, EBML)
@@ -1554,23 +1558,16 @@
/* Set size of memory from 1MB to TopMem */
Subtract(TOM1, 0x100000, DMLL)
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB)
DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the
BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB)
/* Reserve the "BIOS" space */
- Store(PBLN,PBML)
+ If(LNotEqual(TOM2, 0x00000000)){
+ Store(0x100000000,DMHB)
/* DRAM from 4GB to TopMem2 */
+ Subtract(TOM2, 0x100000000, DMHL)
+ Subtract(TOM2, 0x1, DMHM)
}
- Else { /* Otherwise, put the BIOS just below
16EB */
- ShiftLeft(PBAD,16,EBMB) /*
Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
+ /* Put the BIOS just below 4GB */
+ Store(PBAD,PBMB) /*
Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+
Return(CRES) /* note to change the Name buffer
*/
} /* end of Method(_SB.PCI0._CRS) */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
(Arbeitskopie)
@@ -89,6 +89,31 @@
outb(byte, 0xC52);
}
+/*
+ * This is a totally gross hack to be able to use pci_{read,write}_config*
+ * early during boot when the device tree is not yet set up completely.
+ */
+void devicetree_early_fixup(struct device *dev)
+{
+ struct bus *pbus = dev->bus;
+ while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
+ if (pbus == pbus->dev->bus)
+ break;
+ pbus = pbus->dev->bus;
+ }
+ if (ops_pci_bus(pbus)) {
+ printk_info("%s not needed\n", __func__);
+ return;
+ }
+ if (pbus && pbus->dev && pbus->dev->ops) {
+ printk_info("%s fixing up root bus pci ops\n", __func__);
+ pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1;
+ return;
+ }
+ printk_info("%s failed\n", __func__);
+ return;
+}
+
/********************************************************
* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
@@ -97,32 +122,25 @@
static void get_ide_dma66()
{
u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
- struct bus pbus;
+ struct device *sm_dev;
+ struct device *ide_dev;
+ printk_info("%s.\n", __func__);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ devicetree_early_fixup(sm_dev);
- byte =
- pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0xA9);
+ byte = pci_read_config8(sm_dev, 0xA9);
byte |= (1 << 5); /* Set Gpio9 as input */
- pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0xA9, byte);
+ pci_write_config8(sm_dev, 0xA9, byte);
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte =
- pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
- ide_dev->path.pci.devfn, 0x56);
+ byte = pci_read_config8(ide_dev, 0x56);
byte &= ~(7 << 0);
- if ((1 << 5) & pci_cf8_conf1.
- read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
- 0xAA))
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
byte |= 2 << 0; /* mode 2 */
else
byte |= 5 << 0; /* mode 5 */
- pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
- ide_dev->path.pci.devfn, 0x56, byte);
+ pci_write_config8(ide_dev, 0x56, byte);
}
/*
@@ -133,7 +151,6 @@
u8 byte;
u16 word;
device_t sm_dev;
- struct bus pbus;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -156,12 +173,9 @@
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word =
- pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56);
+ word = pci_read_config16(sm_dev, 0x56);
word |= 1 << 7;
- pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56, word);
+ pci_write_config16(sm_dev, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
@@ -197,12 +211,12 @@
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*************************************************/
-void dbm690t_enable(device_t dev)
+void mb_enable(device_t dev)
{
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
- printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev);
+ printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n",
dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
@@ -264,6 +278,6 @@
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD DBM690T Mainboard")
- .enable_dev = dbm690t_enable,
+ CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = mb_enable,
};
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
(Arbeitskopie)
@@ -32,6 +32,8 @@
#define DIMM0 0x50
#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
#define ICS951462_ADDRESS 0x69
#define SMBUS_HUB 0x71
@@ -137,7 +139,7 @@
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
- :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
+ :"a" (bist), "b"(cpu_init_detectedx)); /*
inputs */
fallback_image:
post_code(0x25);
@@ -157,14 +159,14 @@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
+ static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
};
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
- struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +
DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +
+ DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
-
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
@@ -181,7 +183,7 @@
report_bist_failure(bist);
printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
- setup_dbm690t_resource_map();
+ setup_mb_resource_map();
setup_coherent_ht_domain();
Index: LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Arbeitskopie)
@@ -37,6 +37,7 @@
#include <part/init_timer.h>
#include <boot/elf.h>
#include <romfs.h>
+#include "../southbridge/amd/rs690/rs690.h"
/**
* @brief Main function of the DRAM part of coreboot.
@@ -50,6 +51,7 @@
void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
+ device_t nb_dev;
post_code(0x80);
@@ -84,6 +86,8 @@
dev_initialize();
post_code(0x89);
+ nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
/* Now that we have collected all of our information
* write our configuration tables.
*/
Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
(Arbeitskopie)
@@ -1,6 +1,8 @@
#ifndef __ASM_MPSPEC_H
#define __ASM_MPSPEC_H
+#include <device/device.h>
+
#if HAVE_MP_TABLE==1
/*
Index: LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
(Arbeitskopie)
@@ -7,9 +7,12 @@
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
__COMPRESSION__
-option ROM_SIZE=1024*1024
+option ROM_SIZE = 1024*1024 - 54784
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
--
http://www.hailfinger.org/
Index: LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/southbridge/amd/rs690/rs690_cmn.c
(Arbeitskopie)
@@ -63,8 +63,8 @@
/*get BAR3 base address for nbcfg0x1c */
u32 addr = pci_read_config32(nb_dev, 0x1c);
- /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr,
dev->bus->secondary,
- dev->path.pci.devfn);*/
+ printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr,
dev->bus->secondary,
+ dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
dev->path.pci.devfn << 12 | reg_pos;
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/Config.lb (Arbeitskopie)
@@ -195,7 +195,7 @@
#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not
supported), 6: x16
chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on
- chip cpu/amd/socket_S1G1
+ chip cpu/amd/socket_AM2
device apic 0 on end
end
end
@@ -211,7 +211,7 @@
end
end
device pci 2.0 on end # PCIE P2P bridge
(external graphics) 0x7913
- device pci 3.0 off end # PCIE P2P
bridge 0x791b
+ #device pci 3.0 off end # PCIE P2P
bridge 0x791b
device pci 4.0 on end # PCIE P2P bridge
0x7914
device pci 5.0 on end # PCIE P2P bridge
0x7915
device pci 6.0 on end # PCIE P2P bridge
0x7916
@@ -255,9 +255,9 @@
device pci 14.3 on # LPC 0x438d
chip superio/ite/it8712f
device pnp 2e.0 off #
Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
+ #io 0x60 = 0x3f0
+ #irq 0x70 = 6
+ #drq 0x74 = 2
end
device pnp 2e.1 on #
Com1
io 0x60 = 0x3f8
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/irq_tables.c
(Arbeitskopie)
@@ -54,7 +54,7 @@
extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
-extern unsigned long sbdn_sb600;
+extern u32 sbdn_sb600;
unsigned long write_pirq_routing_table(unsigned long addr)
{
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/resourcemap.c
(Arbeitskopie)
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-static void setup_dbm690t_resource_map(void)
+static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
/* Careful set limit registers before base registers which
contain the enables */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/acpi/dsdt.asl
(Arbeitskopie)
@@ -33,8 +33,8 @@
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
- Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
- Name(PBLN, 0x0) /* Length of BIOS area */
+ Name(PBAD, 0xFFF00000) /* Address of BIOS area (If TOM2 != 0, Addr >>
16) */
+ Name(PBLN, 0x00100000) /* Length of BIOS area (1 MB hardcoded) */
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
@@ -273,7 +273,7 @@
* The 8 comes from 8 functions per device, and 4096
bytes per function config space
*/
Offset(0x00090024), /* Byte offset to SATA register
24h - Bus 0, Device 18, Function 0 */
- STB5, 32,
+ STB5, 32, /* Address of SATA_BAR5 */
Offset(0x00098042), /* Byte offset to OHCI0
register 42h - Bus 0, Device 19, Function 0 */
PT0D, 1,
PT1D, 1,
@@ -297,7 +297,9 @@
P92E, 1, /* Port92 decode enable */
}
- OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+ /* FIXME: EVIL HACK. SB5 address is hardcoded to 0xfc409000 in
the hope the OS won't touch it. */
+ /*OperationRegion(SB5, SystemMemory, 0xfc409000, 0x1000)*/ /*
SATA_BAR5 (ABAR) */
+ OperationRegion(SB5, SystemMemory, STB5, 0x1000) /* SATA_BAR5
(ABAR) */
Field(SB5, AnyAcc, NoLock, Preserve)
{
/* Port 0 */
@@ -308,9 +310,9 @@
, 3,
P0BY, 1,
Offset(0x128), /* Port 0 Serial ATA status */
- P0DD, 4,
+ P0DD, 4, /* Port 0 Device Detection
(DET) */
, 4,
- P0IS, 4,
+ P0IS, 4, /* Port 0 Interface Power
Management (IPM) */
Offset(0x12C), /* Port 0 Serial ATA control */
P0DI, 4,
Offset(0x130), /* Port 0 Serial ATA error */
@@ -1493,23 +1495,24 @@
Memory32Fixed(READONLY, 0x000E0000, 0x00020000,
RDBS) /* BIOS ROM area */
/* DRAM Memory from 1MB to TopMem */
- Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)
/* 1MB to TopMem */
+ Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)
/* 1MB to TopMem, the length is filled out when DMLL is calculated */
/* BIOS space just below 4GB */
DWORDMemory(
ResourceProducer, PosDecode, MinFixed,
MaxFixed, Cacheable, ReadWrite,
0x00, /* Granularity
*/
0x00000000, /* Min */
- 0x00000000, /* Max */
+ 0xFFFFFFFF, /* Max */
0x00000000, /* Translation
*/
0x00000000, /* Max-Min,
RLEN */
,,
- PCBM
+ PCBM,
+ AddressRangeReserved
)
/* DRAM memory from 4GB to TopMem2 */
QWORDMemory(ResourceProducer, PosDecode,
MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0xFFFFFFFF, /* Granularity
*/
+ 0x3FFFFFFF, /* Granularity
must be 1 GB or lower! Due to hoisting, RLEN will always be 2k+1 GB */
0x00000000, /* Min */
0x00000000, /* Max */
0x00000000, /* Translation
*/
@@ -1543,6 +1546,7 @@
CreateQWordField(CRES, ^DMHI._MIN, DMHB)
CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+ CreateQWordField(CRES, ^DMHI._MAX, DMHM)
CreateQWordField(CRES, ^PEBM._MIN, EBMB)
CreateQWordField(CRES, ^PEBM._LEN, EBML)
@@ -1554,23 +1558,16 @@
/* Set size of memory from 1MB to TopMem */
Subtract(TOM1, 0x100000, DMLL)
- /*
- * If(LNotEqual(TOM2, 0x00000000)){
- * Store(0x100000000,DMHB)
DRAM from 4GB to TopMem2
- * Subtract(TOM2, 0x100000000, DMHL)
- * }
- */
-
- /* If there is no memory above 4GB, put the
BIOS just below 4GB */
- If(LEqual(TOM2, 0x00000000)){
- Store(PBAD,PBMB)
/* Reserve the "BIOS" space */
- Store(PBLN,PBML)
+ If(LNotEqual(TOM2, 0x00000000)){
+ Store(0x100000000,DMHB)
/* DRAM from 4GB to TopMem2 */
+ Subtract(TOM2, 0x100000000, DMHL)
+ Subtract(TOM2, 0x1, DMHM)
}
- Else { /* Otherwise, put the BIOS just below
16EB */
- ShiftLeft(PBAD,16,EBMB) /*
Reserve the "BIOS" space */
- Store(PBLN,EBML)
- }
+ /* Put the BIOS just below 4GB */
+ Store(PBAD,PBMB) /*
Reserve the "BIOS" space */
+ Store(PBLN,PBML)
+
Return(CRES) /* note to change the Name buffer
*/
} /* end of Method(_SB.PCI0._CRS) */
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/mainboard.c
(Arbeitskopie)
@@ -89,6 +89,31 @@
outb(byte, 0xC52);
}
+/*
+ * This is a totally gross hack to be able to use pci_{read,write}_config*
+ * early during boot when the device tree is not yet set up completely.
+ */
+void devicetree_early_fixup(struct device *dev)
+{
+ struct bus *pbus = dev->bus;
+ while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
+ if (pbus == pbus->dev->bus)
+ break;
+ pbus = pbus->dev->bus;
+ }
+ if (ops_pci_bus(pbus)) {
+ printk_info("%s not needed\n", __func__);
+ return;
+ }
+ if (pbus && pbus->dev && pbus->dev->ops) {
+ printk_info("%s fixing up root bus pci ops\n", __func__);
+ pbus->dev->ops->ops_pci_bus = &pci_cf8_conf1;
+ return;
+ }
+ printk_info("%s failed\n", __func__);
+ return;
+}
+
/********************************************************
* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
@@ -97,32 +122,25 @@
static void get_ide_dma66()
{
u8 byte;
- /*u32 sm_dev, ide_dev; */
- device_t sm_dev, ide_dev;
- struct bus pbus;
+ struct device *sm_dev;
+ struct device *ide_dev;
+ printk_info("%s.\n", __func__);
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ devicetree_early_fixup(sm_dev);
- byte =
- pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0xA9);
+ byte = pci_read_config8(sm_dev, 0xA9);
byte |= (1 << 5); /* Set Gpio9 as input */
- pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0xA9, byte);
+ pci_write_config8(sm_dev, 0xA9, byte);
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
- byte =
- pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
- ide_dev->path.pci.devfn, 0x56);
+ byte = pci_read_config8(ide_dev, 0x56);
byte &= ~(7 << 0);
- if ((1 << 5) & pci_cf8_conf1.
- read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
- 0xAA))
+ if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
byte |= 2 << 0; /* mode 2 */
else
byte |= 5 << 0; /* mode 5 */
- pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
- ide_dev->path.pci.devfn, 0x56, byte);
+ pci_write_config8(ide_dev, 0x56, byte);
}
/*
@@ -133,7 +151,6 @@
u8 byte;
u16 word;
device_t sm_dev;
- struct bus pbus;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -156,12 +173,9 @@
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word =
- pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56);
+ word = pci_read_config16(sm_dev, 0x56);
word |= 1 << 7;
- pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56, word);
+ pci_write_config16(sm_dev, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);
@@ -197,12 +211,12 @@
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*************************************************/
-void dbm690t_enable(device_t dev)
+void mb_enable(device_t dev)
{
struct mainboard_config *mainboard =
(struct mainboard_config *)dev->chip_info;
- printk_info("Mainboard DBM690T Enable. dev=0x%p\n", dev);
+ printk_info("Mainboard " MAINBOARD_PART_NUMBER " Enable. dev=%p\n",
dev);
#if (CONFIG_GFXUMA == 1)
msr_t msr, msr2;
@@ -264,6 +278,6 @@
}
struct chip_operations mainboard_ops = {
- CHIP_NAME("AMD DBM690T Mainboard")
- .enable_dev = dbm690t_enable,
+ CHIP_NAME(MAINBOARD_VENDOR " " MAINBOARD_PART_NUMBER " Mainboard")
+ .enable_dev = mb_enable,
};
Index: LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
(Arbeitskopie)
@@ -32,6 +32,8 @@
#define DIMM0 0x50
#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
#define ICS951462_ADDRESS 0x69
#define SMBUS_HUB 0x71
@@ -137,7 +139,7 @@
normal_image:
post_code(0x23);
__asm__ volatile ("jmp __normal_image": /* outputs */
- :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
+ :"a" (bist), "b"(cpu_init_detectedx)); /*
inputs */
fallback_image:
post_code(0x25);
@@ -157,14 +159,14 @@
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
+ static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
};
int needs_reset = 0;
u32 bsp_apicid = 0;
msr_t msr;
struct cpuid_result cpuid1;
- struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +
DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE +
+ DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
-
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
@@ -181,7 +183,7 @@
report_bist_failure(bist);
printk_debug("bsp_apicid=0x%x\n", bsp_apicid);
- setup_dbm690t_resource_map();
+ setup_mb_resource_map();
setup_coherent_ht_domain();
Index: LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/boot/hardwaremain.c (Arbeitskopie)
@@ -37,6 +37,7 @@
#include <part/init_timer.h>
#include <boot/elf.h>
#include <romfs.h>
+#include "../southbridge/amd/rs690/rs690.h"
/**
* @brief Main function of the DRAM part of coreboot.
@@ -50,6 +51,7 @@
void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
+ device_t nb_dev;
post_code(0x80);
@@ -84,6 +86,8 @@
dev_initialize();
post_code(0x89);
+ nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+ enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
/* Now that we have collected all of our information
* write our configuration tables.
*/
Index: LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/src/arch/i386/include/arch/smp/mpspec.h
(Arbeitskopie)
@@ -1,6 +1,8 @@
#ifndef __ASM_MPSPEC_H
#define __ASM_MPSPEC_H
+#include <device/device.h>
+
#if HAVE_MP_TABLE==1
/*
Index: LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
===================================================================
--- LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
(Revision 4074)
+++ LinuxBIOSv2-asus_m2a-vm/targets/amd/dbm690t/Config-abuild.lb
(Arbeitskopie)
@@ -7,9 +7,12 @@
option CROSS_COMPILE="CROSS_PREFIX"
option HOSTCC="CROSS_HOSTCC"
+option DEFAULT_CONSOLE_LOGLEVEL = 9
+option MAXIMUM_CONSOLE_LOGLEVEL = 9
+
__COMPRESSION__
-option ROM_SIZE=1024*1024
+option ROM_SIZE = 1024*1024 - 54784
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x20000
--
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