Hello,

As seen in the specs these 2 chips accept CE (Chip Erase) opcodes 60 and C7.
Below a patch to fix flashrom accordingly. Also available in attachment.

Make good use of it.

Signed-off-by: Stephan Guilloux <[email protected]>
Index: flashrom/flashchips.c
===================================================================
--- flashrom/flashchips.c       (révision 4138)
+++ flashrom/flashchips.c       (copie de travail)
@@ -806,7 +806,7 @@
                .page_size      = 256,
                .tested         = TEST_UNTESTED,
                .probe          = probe_spi_rdid,
-               .erase          = spi_chip_erase_c7,
+               .erase          = spi_chip_erase_60_c7,
                .write          = spi_chip_write,
                .read           = spi_chip_read,
        },
@@ -820,7 +820,7 @@
                .page_size      = 256,
                .tested         = TEST_UNTESTED,
                .probe          = probe_spi_rdid,
-               .erase          = spi_chip_erase_c7,
+               .erase          = spi_chip_erase_60_c7,
                .write          = spi_chip_write,
                .read           = spi_chip_read,
        },
Index: flashrom/flashchips.c
===================================================================
--- flashrom/flashchips.c	(révision 4138)
+++ flashrom/flashchips.c	(copie de travail)
@@ -806,7 +806,7 @@
 		.page_size	= 256,
 		.tested		= TEST_UNTESTED,
 		.probe		= probe_spi_rdid,
-		.erase		= spi_chip_erase_c7,
+		.erase		= spi_chip_erase_60_c7,
 		.write		= spi_chip_write,
 		.read		= spi_chip_read,
 	},
@@ -820,7 +820,7 @@
 		.page_size	= 256,
 		.tested		= TEST_UNTESTED,
 		.probe		= probe_spi_rdid,
-		.erase		= spi_chip_erase_c7,
+		.erase		= spi_chip_erase_60_c7,
 		.write		= spi_chip_write,
 		.read		= spi_chip_read,
 	},
-- 
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot

Reply via email to